Wee5, Lecture1: Sequential Verilog
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Table of Contents
Sequential Verilog
Variables
Continuous assignment
Example: A comparator
Comparator example (con’t)
always block
always example
always example
Incomplete trigger or incomplete assignment
A better way...
if
if: Another way
case
case: A better way
default case
case (con’t)
casez and casex
casex example
for
Verilog while/repeat/forever
Sequential Verilog
8-bit register with synchronous reset
N-bit register with asynchronous reset
Shift-register
Blocking and non-blocking assignments
Swap (cont’d)
Non-blocking assignment
Counter
Author:
Chris Diorio
Email:
diorio@cs.washington.edu
Home Page:
http://www.cs.washington.edu/education/courses/467/99au/