Numbers

• 14

  • Decimal number

• –14

  • 2’s complement binary of the decimal number

• 12’b0000_0100_0110

  • 12 bit binary number (_ is ignored)

• 3’h046

  • 12 bit hexadecimal number

• Verilog values are unsigned

  • C[4:0] = A[3:0] + B[3:0];
    • if A = 0110 (6) and B = 1010(–6), then C = 10000 (not 00000)
    • B is zero-padded, not sign-extended

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