Simulation versus synthesis (con’t)
Simulation
- Models what a circuit does, not how it does it
- e.g. multiply
- Just say “*”, ignoring the implementation possibilities
- Includes functions and timing
- Allows you to quickly test design options
Synthesis
- Converts your code to a netlist
- Description of interconnected circuit elements
- No timing
- Tools map your netlist to hardware
Verilog and VHDL both simulate and synthesize