Week4, Lecture3: Combinational Verilog
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Table of Contents
Combinational Verilog
Ways of specifying circuits
Hardware description languages (HDLs)
Verilog versus VHDL
Simulation versus synthesis
Simulation versus synthesis (con’t)
Simulation
Structural versus behavioral Verilog
Levels of abstraction
What you will do...
Verilog tips
Xilinx Foundation toolset
Simulation
Hierarchical Schematics
LogicBlox Module Generator
Using Verilog
Modules
Modules
Structural Verilog
Structural full adder
Behavioral Verilog
Data types
Numbers
Operators
Variables
Author:
Chris Diorio
Email:
diorio@cs.washington.edu
Home Page:
http://www.cs.washington.edu/education/courses/467/99au/