Xilinx FPGA Combinational Logic Examples
Key: Functions are limited to 5 inputs (4 even better)
- No limitation on function complexity
Examples:
- 5-input parity generator implemented with 1 CLB F = (A xor B xor C xor D xor E)’
- 2-bit comparator: A B = C D or A B > C D implemented with 1 CLB (GT) F = A C' + A B D' + B C' D' (EQ) G = A' B' C' D' + A' B C' D + A B' C D' + A B C D