The real world

• Use edge-triggered or master-slave flip-flops

  • Integrated circuit design sometimes uses latches

• Obey basic rules for correct timing

  • Clock all flip-flops synchronously
  • Clock all flip-flops on the same clock edge

• Ensure synchronous clocking

  • Match the delays through your clock buffers
    • Match the capacitance each clock buffer must drive

• Don't gate or turn off the clock

• Use synchronous clear and preset where possible

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