DES using an ASIC

• How?

  • A single ASIC
  • Include glue logic in ASIC

• Advantages

  • Fast throughput
    • Pipelined logic
    • 50 – 300 MHz clock
  • Low parts cost for volume production
  • Moderate design cost
    • Debug using FPGAs
    • Synthesize to an ASIC

• Disadvantages

  • Difficult to change algorithm or fix design errors
    • Redesign chip

LSI Logic G10 ASIC design flow

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