Homework Set 4
DUE: Oct 29,1999, 9:30 am
Collaboration Policy:
Unless otherwise noted, you may collaborate with other
CSE467 students on the homework assignments. Do not look at homework or
exam solutions from previous years. You must spend at least 15 minutes
working on a problem before seeking assistance. Collaboration means that
you may discuss the problems and make notes during the discussion, but
you may not look at other student’s work when writing up your homework.
Your homework represents your own work—the homework must show that you
understand the material and have worked as an individual on every problem.
You may not divide up the task of doing the problem sets in the interpretation
of collaboration. You may discuss lecture material with anyone.
Late Homework Policy:
The weekly assignments are due at the beginning of class.
Assignments handed in after class will incur a 10% penalty; the penalty
will increase by 10% for each additional day late.
Reading:
Print and skim the Verilog reference manual posted here
Please show all of your work, and remember, your solutions must be legible. The points for each problem are noted on the problem statement.
1. (20 pts) Design a Verilog module for a register file.
The file should contain eight 8-bit data registers. Your inputs and outputs
should be 8-bit data bytes. Design your register file so that you can read
and write simultaneously (the design should even allow you to read and
write to the same memory location simultaneously—so you will need a register
at the output). Use separate read and write addresses. The write address
indicates which register you write; the read address indicates which register
you read. You will need 2 enable bits, to specify whether you are reading,
writing, both, or neither. Both write and read should be clocked operations.
Construct the registers, decoders, and anything else that you need using
Verilog (you can use Verilog primitives for basic gates). Implement your
design as a Foundation schematic, instance your Verilog modules, write
a simulation script, and simulate your register file. Print your schematics,
simulation results, and anything else you need to show us that your design
works.
2. (20 pts) This problem will be one of our few forays into asynchronous logic. Figure 7.37 (pg. 352 of Katz) shows a 3-bit ripple counter (an up-counter) constructed from T flip-flops. Figure 7.38 shows the timing waveform for this counter. You will modify this counter to count down rather than up, and implement (a) a 3-bit free-running ripple counter, and (b) a 3-bit ripple-down counter with terminal-count detect. This terminal counter is common in hardware design, and works well if (and only if) you know its limitations.
(b) Modify your counter from part (a) so that there is a single output, called terminal_count, that asserts when the counter counts down to 000. Modify your counter design so that your counter counts down to 000, asserts terminal_count, preloads 111, counts down again, etc. You will need a 3-input NOR to assert terminal_count, and another D flip-flop in the preload path to prevent a race condition in the terminal_count output. Consider whether your flip-flops should be falling-edge or rising-edge clock triggered.
Use the Foundation schematic editor to draw your circuit, using D flip-flops from the Xilinx library. Draw a timing diagram (by hand) for your circuit, and determine if there are any hazards in the terminal_count output (i.e. are there any cases when terminal_count temporarily asserts?). Explain your answer. Simulate your circuit, and compare the simulation results with your hand timing diagram. Explain any discrepancies.
(i) Assume the D flip-flops have 10ns propagation delays from clock edge to output, and the NOR gate has a 5ns propagation delay from input to output. What is the delay from a clock edge to terminal_count?
(ii) Assume that you apply the terminal_count signal to the input of another edge-triggered D flip-flop, that uses the same clock signal as your down counter, and that has a 5ns setup time. Assuming your circuit has a maximum clock skew of 5ns, what is the minimum clock period you can use when operating your system?