Lab 3 - CSE 467

For this lab, you should email to Ryan your answers to the questions asked.

Part I: Get a camera and LCD module from Ryan.Look in the above user guides for information on installation. Compile the supplied Quartus project, simulate, and run.

Part II: Look at the top level of the project, taking note of data and control flow. List the following for each module:

1. Name and module designator (U1, V1, etc.)
2. Description of module (in a couple of sentences-- what does it do?)
3. Clock or trigger source for module-- when does it do what it does? Where do the clocks originate in this design?
4. Sources of data and control-- for each module, where does the data and control come from?
5. Sinks (destinations) of data and control-- for each module, where does the data and control go to?

Note: if a module is instantiated more than once for two different purposes, make it clear that you understand how the module is used in each case.

Part III: Analyze the keys and switches-- list what they do. (Some of this is in the documentation, some of this you have to analyse the verilog and datasheets.)

Part IV, EXTRA CREDIT: Testing-- pick a module and write a test fixture for it. Email it to Ryan. In your email, explain which module you are testing and what faults your tester would find.

Your email to Ryan is due at the start of next week's Lab period.

These may be of help:

• Using Library Modules in Verilog Design
• Timing Considerations with Verilog-Based Designs
• Quartus II Simulation with Verilog Designs

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