CSE467 Workload, Grading, and Policies

Catalog Data: CSE467: Advanced Digital Design (3).
Advanced techniques in the design of digital systems. Hardware description languages, combinational and sequential logic synthesis and optimization methods, partitioning, mapping to regular structures. Emphasis on reconfigurable logic as an implementation medium. Memory system design. Digital communication including serial/parallel and synchronous/asynchronous methods. Prerequisites: CSE370 and CSE326.

Course Goals: To provide in-depth understanding of digital systems and their design, from specification and simulation to construction and debugging.

Enrollment:  All students must have completed the prerequisite material (CSE326/CSE370).


Homework: There will be two kinds of homework:

1) Regular homework sets which you will have about a week to complete

2) Short design problems at the end of some lectures, which will be due at the beginning of the next lecture (unless more time is allotted).  You will get 10 points for making a good attempt to solve the problem and another 10 points will be given for correct solutions.  We will not be able to grade every problem – for these you will get full marks for turning in a solution. No late solutions will be accepted.

Your occasional homework assignments are due at the beginning of class on the assigned due date. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late.  Assignments due Friday will be charged 20% if turned in over the weekend, 30% if turned in on Monday, etc.

Assignment problems will sometimes be graded on a random basis. To get full credit for an assignment, you must, of course, turn-in solutions for each assigned problem. Only a subset of the problems will actually be graded in detail. You will not know in advance which problems this will be - so make sure to do all of them.

Please review the assignment solutions carefully before questioning a grade with either the instructor or the teaching assistants.

Labs: There is a lab scheduled every week, with one section meeting Tuesday and the other meeting Thursday.  Some of the labs will be self-contained and you will be able to complete it in the three hour lab time.  Other labs will require extra work to complete.  You will be given a week to complete lab assignments (i.e. until the next lab session).  Labs will be done in groups of two - we will assign groups randomly.

Collaborative Learning: It is well known that students can learn a lot from each other given the chance.  I encourage you to work with each other.  However, I also expect the work you turn in for homework, labs and the design problems to be your own.  That is, even though you may get ideas from other students, you are responsible for understanding it to the point where you can put the design together and get it to work.  I also encourage you to help other students.  However, although it is fine to discuss ideas or help them debug a design, please do not do their work for them.

Exams: There will be a mid-term exam. The final exam will be two hours . Midterm and the final exam will be open notes.

Grading: The course grade will be roughly determined as follows:

I do not grade on the curve.  I'd be delighted if everyone got a 4.0

Cheating Policy: You may work with others to complete homework and lab assignments. It is, of course, in your best interests to contribute as much as you can. If you got substantial help from someone else on an assignment, please make a note to that effect (so they can get extra credit). There will be no collaboration on quizzes and exams. I take cheating very seriously. Any cases will be sent to the cheating committee for prosecution.

Comments to: cse467-webmaster@cs.washington.edu