// The module contains a pipeline register
// The pipeline register provides a buffer that decouples
// one pipeline stage from the next

module pipe_reg(/*AUTOARG*/
  // Outputs
  takingDataIn, dataOut, dataValidOut, 
  // Inputs
  clk, reset, dataIn, dataValidIn, takingDataOut
  );
  parameter WIDTH = 16;
  input clk, reset;
  input [WIDTH-1:0] dataIn;
  input 	    dataValidIn;
  output 	    takingDataIn;
  output [WIDTH-1:0] dataOut;
  output 	     dataValidOut;
  input 	     takingDataOut;

  /*AUTOREG*/
  // Beginning of automatic regs (for this module's undeclared outputs)
  // End of automatics

  // Buffer registers
  reg [WIDTH-1:0] 	A, B;

  reg [1:0] 		state, nxtState;
  parameter 		EMPTY = 2, HALF = 3, FULL = 1;
  assign 		takingDataIn = state[1];
  assign 		dataValidOut = state[0];
  
  wire	transferIn = dataValidIn & takingDataIn;
  wire	transferOut = dataValidOut & takingDataOut;
  
  assign dataOut = takingDataIn ? A : B;
  always @(posedge clk) begin
    if (reset) begin
      state <= EMPTY;
    end else begin
      if (transferIn) begin
	A <= dataIn;
      end
      B <= dataOut;
      state <= nxtState;
    end
  end // always @ (posedge clk)

  always @(*) begin
    nxtState = state;
    case (state) 
      EMPTY: begin
	if (transferIn) nxtState = HALF;
      end
      HALF: begin
	if (transferOut && !transferIn) nxtState = EMPTY;
	else if (transferIn && !transferOut) nxtState = FULL;
      end
      FULL: begin
	if (transferOut) nxtState = HALF;
      end
      default: nxtState = 2'bX;
    endcase // case(state)
  end // always @ (*)

endmodule // pipe_reg