module SRAMInterface( clock, reset, rq_sram_read, rq_sram_write, read_data, write_sram_data, addr_in, sram_addr_out, sram_io, sram_we, sram_oe, sram_ce ); //parameters parameter DATAWIDTH = 8; parameter ADDRWIDTH = 17; //argument direction input clock; input reset; input rq_sram_read; input rq_sram_write; output [DATAWIDTH - 1: 0] read_data; input [DATAWIDTH - 1: 0] write_sram_data; input [ADDRWIDTH - 1: 0] addr_in; //All of the ports connected to the sram chips output [ADDRWIDTH - 1: 0] sram_addr_out; inout [DATAWIDTH - 1: 0] sram_io; output sram_we; output sram_oe; output sram_ce; //Argument types wire clock; wire reset; wire rq_sram_read; wire rq_sram_write; wire [DATAWIDTH - 1: 0] read_data; wire [DATAWIDTH - 1: 0] write_sram_data; wire [ADDRWIDTH - 1: 0] addr_in; wire [ADDRWIDTH - 1: 0] sram_addr_out; wire [DATAWIDTH - 1: 0] sram_io; wire sram_we; wire sram_oe; wire sram_ce; //Internal registers reg write_sram; reg data_reg; reg [ADDRWIDTH - 1: 0] addr_reg; reg [DATAWIDTH - 1: 0] write_data; reg write_we; reg read_oe; //Wire to update internal registers wire next_write_sram; wire next_data_reg; wire [ADDRWIDTH - 1: 0] next_addr_reg; wire [DATAWIDTH - 1: 0] next_write_data; wire [DATAWIDTH - 1: 0] next_write_io; wire next_read_oe; wire next_write_we; assign next_write_sram = rq_sram_write ? 1 : 0; assign next_write_data = rq_sram_write ? write_sram_data : write_data; assign next_write_we = rq_sram_write ? 0 : 1; assign next_write_io = (rq_sram_write || write_sram) ? next_write_data : 8'bz; assign next_addr_reg = (rq_sram_read || rq_sram_write) ? addr_in : addr_reg; assign next_data_reg = rq_sram_read ? 1 : 0; assign next_read_oe = rq_sram_read ? 0 : 1; always @(posedge clock) begin if(reset == 1) begin write_sram = 0; data_reg = 0; end else begin write_sram = next_write_sram; addr_reg = next_addr_reg; write_data = next_write_data; data_reg = next_data_reg; end end always @(negedge clock) begin if(reset == 1) begin write_we = 1; read_oe = 1; end else begin write_we = next_write_we; read_oe = next_read_oe; end end assign read_data = (next_data_reg || data_reg) ? sram_io : 0; assign sram_addr_out = next_addr_reg; assign sram_io = next_write_io; assign sram_oe = read_oe; assign sram_we = write_we; assign sram_ce = 0; endmodule