Synthesis Log
Created on 18:00:46 05/22/04
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Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
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TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : opb_string_simulation.prj
Input Format : mixed
Verilog Include Directory : z:\My_Designs\opb_string_simulation\opb_string_simulation\src
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : opb_string_simulation
Output Format : NGC
Target Device : xcv1000-6bg560
---- Source Options
Top Module Name : opb_string_simulation
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
RAM Extraction : YES
RAM Style : Block
ROM Extraction : YES
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Automatic Register Balancing : No
ROM Style : Auto
Multiplier Style : lut
CASE Implementation Style : Full
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Equivalent register Removal : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
Move First FlipFlop Stage : YES
Move Last FlipFlop Stage : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : YES
Global Optimization : AllClockNets
RTL Output : Yes
Write Timing Constraints : NO
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
Read Cores : YES
Optimize Instantiated Primitives : NO
=========================================================================
WARNING:Xst:1885 - LSO file is empty, default list of libraries is used
=========================================================================
* HDL Compilation *
=========================================================================
Compiling source file ".\..\src\codec_clocks_generator.v"
Module <codec_clocks_generator> compiled
Compiling source file ".\..\src\codec_controller.v"
Module <codec_controller> compiled
Compiling source file ".\..\src\codec_receiver.v"
Module <codec_receiver> compiled
Compiling source file ".\..\src\codec_transmitter.v"
Module <codec_transmitter> compiled
Compiling source file ".\..\src\delay_line.v"
Module <delay_line> compiled
Compiling source file ".\..\src\delay_line_with_pickup.v"
Module <delay_line_with_pickup> compiled
Compiling source file ".\..\src\impulse_generator.v"
Module <impulse_generator> compiled
Compiling source file ".\..\src\mixer.v"
Module <mixer> compiled
Compiling source file ".\..\src\nut_filter.v"
Module <nut_filter> compiled
Compiling source file ".\..\src\opb_string_simulation.v"
Module <opb_string_simulation> compiled
Compiling source file ".\..\src\simulation_control.v"
Module <simulation_control> compiled
Compiling source file ".\..\src\string_control.v"
Module <string_control> compiled
Compiling source file ".\..\src\string_simulation.v"
Module <string_simulation> compiled
Compiling source file ".\..\src\tf_bridge_filter.v"
Module <tf_bridge_filter> compiled
Compiling source file ".\..\src\tf_mixer.v"
Module <tf_mixer> compiled
Compiling source file ".\..\src\tf_nut_filter.v"
Module <tf_nut_filter> compiled
Compiling source file ".\..\src\tf_simulation_control.v"
Compiling source file ".\..\src\bridge_filter.v"
Module <bridge_filter> compiled
Compiling source file ".\..\src\ram_block.v"
Module <ram_block> compiled
No errors in compilation
Analysis of file <opb_string_simulation.prj> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <opb_string_simulation>.
Module <opb_string_simulation> is correct for synthesis.
Analyzing module <string_simulation>.
Module <string_simulation> is correct for synthesis.
Analyzing module <codec_controller>.
Module <codec_controller> is correct for synthesis.
Analyzing module <codec_transmitter>.
.\..\src\codec_transmitter.v line 93: Found Full Case directive in module <codec_transmitter>.
Module <codec_transmitter> is correct for synthesis.
Analyzing module <codec_receiver>.
.\..\src\codec_receiver.v line 87: Found Full Case directive in module <codec_receiver>.
Module <codec_receiver> is correct for synthesis.
Analyzing module <codec_clocks_generator>.
.\..\src\codec_clocks_generator.v line 80: Found Full Case directive in module <codec_clocks_generator>.
.\..\src\codec_clocks_generator.v line 91: Found Full Case directive in module <codec_clocks_generator>.
Module <codec_clocks_generator> is correct for synthesis.
Analyzing module <string_control>.
.\..\src\string_control.v line 213: Found Full Case directive in module <string_control>.
Module <string_control> is correct for synthesis.
Analyzing module <delay_line_with_pickup>.
Module <delay_line_with_pickup> is correct for synthesis.
Analyzing module <delay_line>.
Calling function <next_end_pos>.
Module <delay_line> is correct for synthesis.
Analyzing module <ram_block>.
Module <ram_block> is correct for synthesis.
Analyzing module <impulse_generator>.
.\..\src\impulse_generator.v line 112: Found Full Case directive in module <impulse_generator>.
.\..\src\impulse_generator.v line 144: Found Full Case directive in module <impulse_generator>.
Module <impulse_generator> is correct for synthesis.
Analyzing module <bridge_filter>.
Module <bridge_filter> is correct for synthesis.
Analyzing module <nut_filter>.
Module <nut_filter> is correct for synthesis.
Analyzing module <simulation_control>.
Calling function <get_string_length>.
.\..\src\simulation_control.v line 59: Found Full Case directive in module <simulation_control>.
Calling function <get_pickup_location>.
.\..\src\simulation_control.v line 71: Found Full Case directive in module <simulation_control>.
Calling function <get_pluck_value>.
.\..\src\simulation_control.v line 83: Found Full Case directive in module <simulation_control>.
Calling function <get_pluck_location>.
.\..\src\simulation_control.v line 95: Found Full Case directive in module <simulation_control>.
.\..\src\simulation_control.v line 180: Found Full Case directive in module <simulation_control>.
Enabling task <set_string_length>.
.\..\src\simulation_control.v line 109: Found Full Case directive in module <simulation_control>.
Enabling task <set_pickup_location>.
.\..\src\simulation_control.v line 122: Found Full Case directive in module <simulation_control>.
Enabling task <set_pluck_value>.
.\..\src\simulation_control.v line 135: Found Full Case directive in module <simulation_control>.
Enabling task <set_pluck_location>.
.\..\src\simulation_control.v line 148: Found Full Case directive in module <simulation_control>.
.\..\src\simulation_control.v line 192: Found Full Case directive in module <simulation_control>.
Module <simulation_control> is correct for synthesis.
Analyzing module <mixer>.
.\..\src\mixer.v line 120: Found Full Case directive in module <mixer>.
.\..\src\mixer.v line 145: Found Full Case directive in module <mixer>.
Module <mixer> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ram_block>.
Related source file is .\..\src\ram_block.v.
Found 256x16-bit single-port block RAM for signal <ram>.
-----------------------------------------------------------------------
| mode | write-first | |
| aspect ratio | 256-word x 16-bit | |
| clock | connected to signal <CLK> | rise |
| write enable | connected to signal <WE> | high |
| address | connected to signal <A> | |
| data in | connected to signal <DI> | |
| data out | connected to signal <DO> | |
| ram_style | Block | |
-----------------------------------------------------------------------
Summary:
inferred 1 RAM(s).
Unit <ram_block> synthesized.
Synthesizing Unit <delay_line>.
Related source file is .\..\src\delay_line.v.
WARNING:Xst:1780 - Signal <buffer> is never used or assigned.
Found 8-bit comparator greatequal for signal <$n0000> created at line 52.
Found 8-bit adder for signal <$old_next_end_pos/1/potential_end_pos_3>.
Found 8-bit register for signal <curr_end_pos>.
Summary:
inferred 8 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 1 Comparator(s).
Unit <delay_line> synthesized.
Synthesizing Unit <nut_filter>.
Related source file is .\..\src\nut_filter.v.
Found 16-bit register for signal <DATA_OUT>.
Found 16-bit adder for signal <$n0001> created at line 50.
Found 16-bit register for signal <saved_data>.
Summary:
inferred 32 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
Unit <nut_filter> synthesized.
Synthesizing Unit <bridge_filter>.
Related source file is .\..\src\bridge_filter.v.
WARNING:Xst:646 - Signal <raw_data_out<16:17>> is assigned but never used.
Found 16-bit register for signal <DATA_OUT>.
Found 16-bit subtractor for signal <$n0000> created at line 79.
Found 17-bit adder for signal <$n0001> created at line 54.
Found 16-bit register for signal <curr_input>.
Found 16-bit register for signal <prev_input>.
Found 16-bit register for signal <prev_prev_input>.
Found 18-bit adder for signal <raw_data_out>.
Summary:
inferred 64 D-type flip-flop(s).
inferred 3 Adder/Subtracter(s).
Unit <bridge_filter> synthesized.
Synthesizing Unit <impulse_generator>.
Related source file is .\..\src\impulse_generator.v.
Found 16-bit register for signal <OUTPUT>.
Found 9-bit comparator equal for signal <$n0000> created at line 151.
Found 9-bit comparator greatequal for signal <$n0003> created at line 116.
Found 9-bit adder for signal <$n0008> created at line 148.
Found 9-bit register for signal <curr_pos>.
Found 9-bit register for signal <peak_pos_buf>.
Found 16-bit register for signal <peak_val_buf>.
Found 9-bit register for signal <size_buf>.
Found 1-bit register for signal <state>.
Found 34 1-bit 2-to-1 multiplexers.
Summary:
inferred 60 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
inferred 34 Multiplexer(s).
Unit <impulse_generator> synthesized.
Synthesizing Unit <delay_line_with_pickup>.
Related source file is .\..\src\delay_line_with_pickup.v.
WARNING:Xst:647 - Input <SIZE<0>> is never used.
Found 8-bit subtractor for signal <post_pickup_size>.
Summary:
inferred 1 Adder/Subtracter(s).
Unit <delay_line_with_pickup> synthesized.
Synthesizing Unit <codec_clocks_generator>.
Related source file is .\..\src\codec_clocks_generator.v.
Found 4-bit adder for signal <$old_next_neg_counter_2>.
Found 4-bit adder for signal <$old_next_pos_counter_1>.
Found 8-bit up accumulator for signal <divider>.
Found 4-bit register for signal <neg_counter>.
Found 1-bit register for signal <neg_strobe>.
Found 4-bit register for signal <pos_counter>.
Found 1-bit register for signal <pos_strobe>.
Found 1-bit register for signal <prev_mclk>.
Summary:
inferred 1 Accumulator(s).
inferred 7 D-type flip-flop(s).
inferred 2 Adder/Subtracter(s).
Unit <codec_clocks_generator> synthesized.
Synthesizing Unit <codec_receiver>.
Related source file is .\..\src\codec_receiver.v.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 4 |
| Outputs | 4 |
| Clock | CLK (rising_edge) |
| Reset | RST (positive) |
| Reset type | synchronous |
| Reset State | 0001 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 32-bit register for signal <DATA>.
Found 4-bit adder for signal <$n0008>.
Found 1-bit register for signal <bick_buf>.
Found 4-bit register for signal <counter>.
Found 1-bit register for signal <lrck_buf>.
Found 1-bit register for signal <prev_bick>.
Found 1-bit register for signal <prev_lrck>.
Found 32 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Finite State Machine(s).
inferred 40 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 32 Multiplexer(s).
Unit <codec_receiver> synthesized.
Synthesizing Unit <codec_transmitter>.
Related source file is .\..\src\codec_transmitter.v.
Found finite state machine <FSM_1> for signal <state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 4 |
| Outputs | 4 |
| Clock | CLK (rising_edge) |
| Reset | RST (positive) |
| Reset type | synchronous |
| Reset State | 0001 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 32-bit shifter logical left for signal <$n0006>.
Found 4-bit adder for signal <$n0008>.
Found 1-bit register for signal <bick_buf>.
Found 4-bit register for signal <counter>.
Found 1-bit register for signal <prev_bick>.
Found 1-bit register for signal <prev_lrck>.
Found 32-bit register for signal <shift_reg>.
Summary:
inferred 1 Finite State Machine(s).
inferred 39 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 1 Combinational logic shifter(s).
Unit <codec_transmitter> synthesized.
Synthesizing Unit <mixer>.
Related source file is .\..\src\mixer.v.
WARNING:Xst:646 - Signal <left_channel_sum<16:19>> is assigned but never used.
WARNING:Xst:646 - Signal <right_channel_sum<16:19>> is assigned but never used.
Found finite state machine <FSM_2> for signal <state>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 7 |
| Inputs | 4 |
| Outputs | 3 |
| Clock | CLK (rising_edge) |
| Reset | RST (positive) |
| Reset type | synchronous |
| Reset State | 001 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit register for signal <LEFT_CHANNEL>.
Found 16-bit register for signal <RIGHT_CHANNEL>.
Found 17-bit adder for signal <$n0002> created at line 190.
Found 18-bit adder for signal <$n0003> created at line 190.
Found 19-bit adder for signal <$n0004> created at line 190.
Found 17-bit adder for signal <$n0005> created at line 197.
Found 18-bit adder for signal <$n0006> created at line 197.
Found 19-bit adder for signal <$n0007> created at line 197.
Found 20-bit adder for signal <left_channel_sum>.
Found 20-bit adder for signal <right_channel_sum>.
Found 16-bit register for signal <string0_buffer>.
Found 1-bit register for signal <string0_latched>.
Found 16-bit register for signal <string1_buffer>.
Found 1-bit register for signal <string1_latched>.
Found 16-bit register for signal <string2_buffer>.
Found 1-bit register for signal <string2_latched>.
Found 16-bit register for signal <string3_buffer>.
Found 1-bit register for signal <string3_latched>.
Found 96 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Finite State Machine(s).
inferred 100 D-type flip-flop(s).
inferred 8 Adder/Subtracter(s).
inferred 96 Multiplexer(s).
Unit <mixer> synthesized.
Synthesizing Unit <simulation_control>.
Related source file is .\..\src\simulation_control.v.
WARNING:Xst:647 - Input <CTRL_ADDR<6:7>> is never used.
Found 36-bit register for signal <PLUCK_LOCATIONS>.
Found 32-bit register for signal <PICKUP_LOCATIONS>.
Found 1-bit register for signal <CTRL_ACK>.
Found 4-bit register for signal <PLUCK_STROBES>.
Found 36-bit register for signal <STRING_LENGTHS>.
Found 32-bit register for signal <CTRL_DATA_OUT>.
Found 1-bit register for signal <MASTER_ENABLE>.
Found 64-bit register for signal <PLUCK_VALUES>.
Found 32-bit register for signal <dummy_register>.
Found 8-bit 4-to-1 multiplexer for signal <get_pickup_location/1/get_pickup_location>.
Found 9-bit 4-to-1 multiplexer for signal <get_pluck_location/1/get_pluck_location>.
Found 16-bit 4-to-1 multiplexer for signal <get_pluck_value/1/get_pluck_value>.
Found 9-bit 4-to-1 multiplexer for signal <get_string_length/1/get_string_length>.
Summary:
inferred 238 D-type flip-flop(s).
inferred 42 Multiplexer(s).
Unit <simulation_control> synthesized.
Synthesizing Unit <string_control>.
Related source file is .\..\src\string_control.v.
Found finite state machine <FSM_3> for signal <state>.
-----------------------------------------------------------------------
| States | 6 |
| Transitions | 10 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | CLK (rising_edge) |
| Reset | RST (positive) |
| Reset type | synchronous |
| Reset State | 000001 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 16-bit register for signal <SAMPLE>.
Found 16-bit adder for signal <$n0002> created at line 250.
Found 16-bit register for signal <l_sample>.
Found 16-bit register for signal <r_sample>.
Found 8-bit subtractor for signal <rg_pickup_location>.
Found 9-bit subtractor for signal <rp_peak_pos>.
Found 82 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Finite State Machine(s).
inferred 48 D-type flip-flop(s).
inferred 3 Adder/Subtracter(s).
inferred 82 Multiplexer(s).
Unit <string_control> synthesized.
Synthesizing Unit <codec_controller>.
Related source file is .\..\src\codec_controller.v.
Found 32-bit register for signal <RECEIVED_SAMPLE>.
Found 1-bit register for signal <lrck_buf>.
Found 1-bit register for signal <prev_LRCK>.
Found 128-bit register for signal <send_sample_regs>.
Summary:
inferred 162 D-type flip-flop(s).
Unit <codec_controller> synthesized.
Synthesizing Unit <string_simulation>.
Related source file is .\..\src\string_simulation.v.
Unit <string_simulation> synthesized.
Synthesizing Unit <opb_string_simulation>.
Related source file is .\..\src\opb_string_simulation.v.
WARNING:Xst:646 - Signal <OPB_seqAddr_Reg> is assigned but never used.
Found 32-bit register for signal <OPB_ABus_Reg>.
Found 4-bit register for signal <OPB_BE_Reg>.
Found 32-bit register for signal <OPB_DBus_Reg>.
Found 1-bit register for signal <OPB_RNW_Reg>.
Found 1-bit register for signal <OPB_select_Reg>.
Summary:
inferred 70 D-type flip-flop(s).
Unit <opb_string_simulation> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 10
# RAMs : 16
256x16-bit single-port block RAM : 16
# Registers : 450
8-bit register : 16
1-bit register : 333
32-bit register : 10
4-bit register : 9
16-bit register : 58
9-bit register : 24
# Accumulators : 1
8-bit up accumulator : 1
# Multiplexers : 63
2-to-1 multiplexer : 59
16-bit 4-to-1 multiplexer : 1
8-bit 4-to-1 multiplexer : 1
9-bit 4-to-1 multiplexer : 2
# Logic shifters : 4
32-bit shifter logical left : 4
# Adders/Subtractors : 75
8-bit adder : 16
19-bit adder : 2
9-bit subtractor : 4
16-bit adder : 8
18-bit adder : 6
16-bit subtractor : 4
17-bit adder : 6
9-bit adder : 8
8-bit subtractor : 12
4-bit adder : 7
20-bit adder : 2
# Comparators : 32
8-bit comparator greatequal : 16
9-bit comparator equal : 8
9-bit comparator greatequal : 8
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
Selecting encoding for FSM_3 ...
Optimizing FSM <FSM_3> on signal <state> with one-hot encoding.
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <state> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <opb_string_simulation> ...
Optimizing unit <simulation_control> ...
Optimizing unit <mixer> ...
Optimizing unit <codec_transmitter> ...
Optimizing unit <codec_receiver> ...
Optimizing unit <impulse_generator> ...
Optimizing unit <bridge_filter> ...
Optimizing unit <nut_filter> ...
Optimizing unit <ram_block> ...
Optimizing unit <codec_clocks_generator> ...
Optimizing unit <delay_line> ...
Optimizing unit <codec_controller> ...
Optimizing unit <delay_line_with_pickup> ...
Optimizing unit <string_control> ...
Optimizing unit <string_simulation> ...
Loading device for application Xst from file 'v1000.nph' in environment C:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block opb_string_simulation, actual ratio is 15.
FlipFlop ss/sc3/state_FFd4 has been replicated 3 time(s)
FlipFlop ss/sc2/state_FFd4 has been replicated 3 time(s)
FlipFlop ss/sc1/state_FFd4 has been replicated 3 time(s)
FlipFlop ss/sc0/state_FFd4 has been replicated 3 time(s)
FlipFlop ss/sc3/r_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc3/l_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc2/r_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc2/l_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc1/r_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc1/l_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc0/r_plucker/state has been replicated 1 time(s)
FlipFlop ss/sc0/l_plucker/state has been replicated 1 time(s)
FlipFlop OPB_RNW_Reg has been replicated 1 time(s)
INFO:Xst:1843 - HDL ADVISOR - FlipFlop OPB_RNW_Reg connected to a primary input has been replicated
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : opb_string_simulation.ngr
Top Level Output File Name : opb_string_simulation
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : YES
Design Statistics
# IOs : 118
Macro Statistics :
# RAM : 16
# 256x16-bit single-port block RAM: 16
# Registers : 454
# 1-bit register : 337
# 16-bit register : 58
# 32-bit register : 10
# 4-bit register : 8
# 8-bit register : 17
# 9-bit register : 24
# Multiplexers : 63
# 16-bit 4-to-1 multiplexer : 1
# 2-to-1 multiplexer : 59
# 8-bit 4-to-1 multiplexer : 1
# 9-bit 4-to-1 multiplexer : 2
# Logic shifters : 4
# 32-bit shifter logical left : 4
# Adders/Subtractors : 76
# 16-bit adder : 8
# 16-bit subtractor : 4
# 17-bit adder : 6
# 18-bit adder : 6
# 19-bit adder : 2
# 20-bit adder : 2
# 4-bit adder : 7
# 8-bit adder : 17
# 8-bit subtractor : 12
# 9-bit adder : 8
# 9-bit subtractor : 4
# Comparators : 32
# 8-bit comparator greatequal : 16
# 9-bit comparator equal : 8
# 9-bit comparator greatequal : 8
Cell Usage :
# BELS : 4718
# BUF : 26
# GND : 60
# LUT1 : 295
# LUT2 : 814
# LUT2_D : 1
# LUT2_L : 416
# LUT3 : 472
# LUT3_D : 1
# LUT3_L : 34
# LUT4 : 684
# LUT4_D : 6
# LUT4_L : 12
# MUXCY : 1012
# MUXF5 : 36
# VCC : 67
# XORCY : 782
# FlipFlops/Latches : 2037
# FD : 18
# FDR : 834
# FDR_1 : 3
# FDRE : 978
# FDRS : 132
# FDS : 10
# FDS_1 : 2
# FDSE : 60
# RAMS : 16
# RAMB4_S16 : 16
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 116
# IBUF : 72
# OBUF : 44
=========================================================================
Device utilization summary:
---------------------------
Selected Device : v1000bg560-6
Number of Slices: 1885 out of 12288 15%
Number of Slice Flip Flops: 2037 out of 24576 8%
Number of 4 input LUTs: 2735 out of 24576 11%
Number of bonded IOBs: 116 out of 408 28%
Number of BRAMs: 16 out of 16 100%
Number of GCLKs: 1 out of 4 25%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
OPB_Clk | BUFGP | 2053 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 15.231ns (Maximum Frequency: 65.656MHz)
Minimum input arrival time before clock: 25.278ns
Maximum output required time after clock: 15.245ns
Maximum combinational path delay: 17.336ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OPB_Clk'
Delay: 15.231ns (Levels of Logic = 25)
Source: ss/mix/string2_buffer_14 (FF)
Destination: ss/mix/RIGHT_CHANNEL_0 (FF)
Source Clock: OPB_Clk rising
Destination Clock: OPB_Clk rising
Data Path: ss/mix/string2_buffer_14 to ss/mix/RIGHT_CHANNEL_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 7 1.065 1.755 string2_buffer_14 (string2_buffer_14)
LUT2_L:I0->LO 1 0.573 0.000 Madd__n0005_inst_lut2_271 (Madd__n0005_inst_lut2_27)
MUXCY:S->O 1 0.653 0.000 Madd__n0005_inst_cy_25 (Madd__n0005_inst_cy_25)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_26 (Madd__n0005_inst_cy_26)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_27 (Madd__n0005_inst_cy_27)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_28 (Madd__n0005_inst_cy_28)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_29 (Madd__n0005_inst_cy_29)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_30 (Madd__n0005_inst_cy_30)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_31 (Madd__n0005_inst_cy_31)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_32 (Madd__n0005_inst_cy_32)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_33 (Madd__n0005_inst_cy_33)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_34 (Madd__n0005_inst_cy_34)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_35 (Madd__n0005_inst_cy_35)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_36 (Madd__n0005_inst_cy_36)
MUXCY:CI->O 1 0.044 0.000 Madd__n0005_inst_cy_37 (Madd__n0005_inst_cy_37)
XORCY:CI->O 1 0.418 1.035 Madd__n0005_inst_sum_40 (_n0031<14>)
LUT2_L:I1->LO 1 0.573 0.000 Madd__n0006_inst_lut2_581 (Madd__n0006_inst_lut2_58)
MUXCY:S->O 1 0.653 0.000 Madd__n0006_inst_cy_55 (Madd__n0006_inst_cy_55)
XORCY:CI->O 1 0.418 1.035 Madd__n0006_inst_sum_59 (_n0034<16>)
LUT2_L:I0->LO 1 0.573 0.000 Madd__n0007_inst_lut2_241 (Madd__n0007_inst_lut2_24)
MUXCY:S->O 1 0.653 0.000 Madd__n0007_inst_cy_23 (Madd__n0007_inst_cy_23)
XORCY:CI->O 1 0.418 1.035 Madd__n0007_inst_sum_25 (_n0021<18>)
LUT2_L:I1->LO 1 0.573 0.000 Madd_right_channel_sum_inst_lut2_801 (Madd_right_channel_sum_inst_lut2_80)
MUXCY:S->O 0 0.653 0.000 Madd_right_channel_sum_inst_cy_76 (Madd_right_channel_sum_inst_cy_76)
XORCY:CI->O 1 0.418 1.035 Madd_right_channel_sum_inst_sum_81 (right_channel_sum<0>)
LUT3_L:I2->LO 1 0.573 0.000 Mmux_next_RIGHT_CHANNEL_Result<15>1 (next_RIGHT_CHANNEL<0>)
FDR:D 0.594 RIGHT_CHANNEL_0
----------------------------------------
Total 15.231ns (9.336ns logic, 5.895ns route)
(61.3% logic, 38.7% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
Offset: 25.278ns (Levels of Logic = 6)
Source: OPB_Rst (PAD)
Destination: ss/sc3/nf/saved_data_0 (FF)
Destination Clock: OPB_Clk rising
Data Path: OPB_Rst to ss/sc3/nf/saved_data_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 65 0.768 4.905 OPB_Rst_IBUF (OPB_Rst_IBUF)
BUF:I->O 66 0.573 4.950 OPB_Rst_IBUF_1 (OPB_Rst_IBUF_1)
begin scope: 'ss'
BUF:I->O 92 0.573 6.120 RST_1 (RST_1)
begin scope: 'sc0'
BUF:I->O 93 0.573 6.165 RST_3 (RST_3)
begin scope: 'l_plucker'
FDR:R 0.651 peak_pos_buf_7
----------------------------------------
Total 25.278ns (3.138ns logic, 22.140ns route)
(12.4% logic, 87.6% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
Offset: 15.245ns (Levels of Logic = 5)
Source: OPB_ABus_Reg_0 (FF)
Destination: Sln_DBus<3> (PAD)
Source Clock: OPB_Clk rising
Data Path: OPB_ABus_Reg_0 to Sln_DBus<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 1.065 1.035 OPB_ABus_Reg_0 (OPB_ABus_Reg_0)
LUT4:I0->O 1 0.573 1.035 its_for_me51 (CHOICE1006)
LUT4_D:I0->O 2 0.573 1.206 its_for_me65 (CHOICE1011)
LUT4:I3->O 19 0.573 2.790 its_for_me77 (its_for_me)
LUT3:I0->O 1 0.573 1.035 Sln_DBus<20>1 (Sln_DBus_20_OBUF)
OBUF:I->O 4.787 Sln_DBus_20_OBUF (Sln_DBus<20>)
----------------------------------------
Total 15.245ns (8.144ns logic, 7.101ns route)
(53.4% logic, 46.6% route)
-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay: 17.336ns (Levels of Logic = 5)
Source: OPB_Rst (PAD)
Destination: Sln_DBus<3> (PAD)
Data Path: OPB_Rst to Sln_DBus<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 65 0.768 4.905 OPB_Rst_IBUF (OPB_Rst_IBUF)
LUT4:I3->O 3 0.573 1.332 its_for_me13 (CHOICE994)
LUT4:I2->O 19 0.573 2.790 its_for_me77 (its_for_me)
LUT3:I0->O 1 0.573 1.035 Sln_DBus<20>1 (Sln_DBus_20_OBUF)
OBUF:I->O 4.787 Sln_DBus_20_OBUF (Sln_DBus<20>)
----------------------------------------
Total 17.336ns (7.274ns logic, 10.062ns route)
(42.0% logic, 58.0% route)
=========================================================================
CPU : 42.75 / 43.14 s | Elapsed : 43.00 / 44.00 s
-->
Total memory usage is 125556 kilobytes
Synthesis finished with warnings.