## CSE467 Homework 4

### Distributed: February 4, 2005 Due: Start of Class, February 11, 2005

#### Design:

1. 1. Implement an N-bit A<B comparator using N 4-1 multiplexers only (no other logic). If you're stuck, you may want to find information about Shannon Decomposition. Turn in a drawing that has enough detail that I could build the circuit for any N I choose.

2. In Verilog, write behavioral code to implement a D Flip-Flop with the following characteristics:
a. It has inputs named (CLK,RST,D,CE) and an output named (Q)
b. It latches it's value on the positive edge of the clock
c. It latches it's value only when chip-enable (CE) is high
d. It has an asynchronous reset (it resets to 0 whenever reset is asserted, not just at the clock edge)

3. The Verilog code below represents a 3- bit linear feedback shift register (LFSR). This type of circuit generates a counting sequence of pseudo-random numbers that repeats after 2^n-1 clock cycles, where n is the number of flip-flops in the LFSR. Sketch a schematic diagram of the LFSR circuit using D flip-flop, multiplexer, and logic gate symbols. Simulate the circuit s behavior by loading the pattern 001 into the LFSR and then enabling the register to count. What is the counting sequence? Note the endian is different from the usual convention we've been using in class.

module lfsr (R, L, Clock, Q);
input [0:2] R;
input L, Clock;
output [0:2] Q;
reg [0:2] Q;
always @(posedge Clock)
if (L)
Q <= R;
else
Q <= {Q, Q^Q, Q};
endmodule