CSE467 Homework 2

Distributed: January 14, 2005
Due: Start of Class, January 21, 2005


  1. [Synchronous Logic] Design a three flip-flop counter that counts in the following sequence: 000, 010, 111, 100, 110, 011, 001, and repeat. Verify that your implementation is self-starting. Turn in your work and a drawing which shows the 3 D-FFs and the gate logic to connect them.

  2. [Verilog/FSM] Design a finite state machine that has one input (X) and two outputs (Z1 and Z2). The first output Z1 is 1 when the input sequence 101 is observed, provided the sequence 011 has never been seen. The second output Z2 is 1 every time the input 011 is observed. Note that Z1=1 and Z2=1 can never occur.
    1. Draw the state diagram for this FSM (the minimum number of states if using a Mealy machine is eight).
    2. Code the state machine in Verilog. Use the “two always block” design as seen in the lecture notes and in lab 1.

  3. [Active-HDL] In Active-HDL, design a sorting network that sorts 4 8-bit numbers. You may want to design a component that sorts 2 numbers and then use this component in a hierarchical design. You will want to use the comparator you designed in homework 1. You may also want to use the 8-bit MUX we provide. We have provided a test fixture that produces the 4 numbers to be sorted. Turn in your schematics and a printout of the console output.

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