Distributed: January 7, 2005
Due: Start of Class, January 14, 2005
Reverse engineer the circuit shown in this schematic in order to derive a two-level realization:
a. Find the Boolean expression that describes the circuit.
b. Construct the truth table for the function.
c. Write the function in canonical sum-of-products form (little m notation).
d. Simplify the function using K-maps.
In this problem, you will design a comparator using schematics and Verilog. This comparator compares two numbers, A and B, on the input and produces two outputs, A=B and A>B. (A and B are unsigned numbers throughout this exercise.)
a. Find the minimal 2-level circuit implementation for these two functions. First design a component using gates for this comparator using Active-HDL.Then design the component using Verilog and continuous assignment. (Use different names for the two components.) Use the text fixture hw1a_tf.v to test your components. Print your schematic, Verilog code and console output from the simulations.
b. Now design two 8-bit comparators, one using schematics and one using structural Verilog, using four of your 2-bit comparators. Use the test fixture hw1b_tf.v to test your components. Print your schematic, Verilog code and console output from the simulations.