UW CSE
Winter 2004
CSE467 Advanced Digital Systems Design
Lab # 6
DUE: You will have until
Late Policy:
Assignments handed in after lab will incur
a 10% penalty for each day late.
Collaboration Policy:
Unless otherwise noted, your group may collaborate with other CSE467 groups on
the lab assignments. Collaboration means that you may discuss the experiments
and make notes during the discussion, but you may not copy another
group’s work when doing the experiments; you may not copy experimental
results from another group; and you may not copy any part of another
group’s lab report. In addition, every individual in a group must understand
the experiments, must participate in the writeup, and should understand the
results. Collaboration does not mean that one person may perform the
experiments and another write up the results – all lab partners must
share equally in all parts of the lab assignment.
Project Groups:
Please see the home Web page for the list of project groups. You will be working as a project team for the
rest of the quarter.
For Lab #5 you designed the codec interface and the wavetable synthesis module. In this lab, you will compile and download this circuit to the XCV1000 board and test/debug it.
All the Xilinx boards and protoboards should be set up identically as described in the Audio_Keypad_Lcd.ucf file. This file is in the Lab5 folder. It defines the FPGA pin connections for the Keypad, the LCD display and the audio Codec board. This Codec board is fixed, but you will have to wire the protoboard with the keypad and the LCD display to the FPGA pins as described in this file. This way, all the boards in the lab will be identical and you will be able to work at any available lab station. (Some Thursday project groups will not have to do this part.) If for some reason, you want to extend the FPGA inputs, please ask first for your own setup.
We have provided a file called scalegen.v in the Lab5 folder that generates a frequency scale. Use this first to test your circuit before using the keypad to generate frequencies for the wavetable to generate. Demonstrate that your circuit works by showing the TA the simulation waveform for your circuit that comprises the scalegen, wavetable and code interface modules. You should use a _top.v module to describe the complete FPGA circuit, and a _test.v module to hold the clock generator, your _top module and (optionally) the codec_tf module.
Have the TA sign off on this before you go to the next part.
TA Signature: _______________________________________________________
You should now compile the _top.v module into a bit file. Pay attention to the warning when you run the synthesis tools. Use the Audio_Keypad_Lcd.ucf from the Lab5 folder.
You may now download the design to your board and see if it works, that is, generates a scale that is pleasing to the ear. If it works, great. If it doesn’t, you have some work to do.
Even if your design works, you must now connect up the oscilloscope to capture the signals MCLK, BICK and LRCK. Turn off the power while you are connecting the probes so you don’t short signals out. You should be careful how you connect the scope probes to these signals (take a look at the TA setup). Also, don’t forget to connect the probe ground signals.
Show your signals to the TA and have him sign off here before you proceed.
TA Signature: ___________________________________________________________________
Using the oscilloscope, you should measure the following values (which can be negative):
a) The frequency of each signal. MCLK:____________ BICK:____________ LRCK:___________
b) The offset from the rising edge of MCLK to the rising edge of BICK:________________________
c) The offset from the rising edge of MCLK to the falling edge of BICK:________________________
d) The offset from the falling edge of BICK to the rising edge of LRCK:________________________
d) The offset from the falling edge of BICK to the falling edge of LRCK:________________________
Now connect the scope to the audio signal itself using the special audio jack that bares the signals. Display this signal on the scope and measure the frequencies of the first 3 notes of the scale:
Note 1 ___________________ Note 2 ____________________ Note 3___________________
TA Signature: _______________________________________________________________________
You will next examine the signals going to the codec using the logic analyzer. We will help you learn how to use the logic analyzer, so when you are ready for this part, come see us. There is also a logic analyzer overview here that you may want to look at for a general idea of how our logic analyzers work. Here are the steps you should take. (This assumes you know how to operate the logic analyzer.)
a) Get a logic analyzer probe cable and plug it into the logic analyzer.
b) Connect logic analyzer probe wires to the signals of interest: MCLK, BICK, LRCK, SDTI1, PDN.
c) Connect the ground wire of the probe to a GND pin.
d) Go to the Module Setup window and enter the signal names along with the logic analyzer probe wire they are connected to.
e) Set the sample frequency to 5ns.
f) The trigger should be set to always trigger.
g) Bring up a waveform window and enter the signals you want to look at.
h) Click RUN and view the waveforms.
Check in particular that values sent to the left and right channels are the same, for all values, both positive and negative, and that the format is correct.
Now go to the trigger setup and setup the logic analyzer to trigger on the rising edge of LRCK.
Demonstrate your logic analyzer setup to the TA and get a sign-off here.
TA Signature: ____________________________________________________________________
Replace the scalegen module with your keypad module and a module that translates keys to frequencies of your choice. Compile and test your design. Demonstrate your design to the TA.
TA Signature: ____________________________________________________________________