CSE467: Advanced Logic Design

Carl Ebeling, Winter 2004


Homework 2

Distributed: Jan. 14 - Due Friday, Jan. 23 (beginning of class)


1. Using Verilog to design a 19-bit (4+4+5+6) carry-select adder.

a) First design a parameterized n-bit adder module that uses a ripple-carry adder. Note that you will need a for loop to describe this adder.

b) Next, define the carry-select adder using several (7) of these n-bit adders. Note that you can use both structural Verilog and behavioral Verilog (assign statements and always blocks) in a module. Choose your signal names wisely to make the connections between the modules. You may use extra levels of hierarchy if you like. You will find a test fixture for this module in the class folder.

c) What is the critical path delay for this adder assuming that a FA delay and a mux delay is 1.

 

2. Using schematics (AND gates and full-adder’s), design a 4-bit unsigned multiplier. You will find the test fixture in the class folder.

 

3. Use Shannon decomposition to find a good implementation of the following functions:

            a) f = a’b’ + b’c’ + a b c

            b) g = bce + b’a’d + b’ace + b’ac’d + bc’d + b’a’e

 

4. Text problem 4.32 (Formal Verification) – Critique the following different ways to solve this problem, discussing advantages and disadvantages. Include in your answer how the method scales to large functions, and whether the method yields a counter-example in the case that the functions are different. (You do not have to solve the problem.)

a) Write both as canonical SOP expressions, and see if the expressions are identical.

b) Enter the functions into a simulator and simulate them to see if they give the same result.

c) Put each through a 2-level logic minimization program and see if the resulting minimized functions are the same.

d) Put each through a multi-level logic minimization program and see if the resulting minimized functions are the same.

e) Generate a new function which is the XOR of the two functions and determine whether it is the function 0 (i.e. FALSE).

f) Represent each as an ordered BDD (same variable ordering) and see if the two BDD’s are identical.


ebeling@cs.washington.edu