CSE467: Advanced Logic Design

Carl Ebeling, Winter 2004

Homework 1

Distributed: Jan 5
Due Wed. Jan 14 beginning of class

Problems from the textbook

1. 2.36
2. 2.41
3. 4.4
4. 4.10
5. 4.12
6. 4.19
7. In this problem, you will design a comparator using schematics and Verilog.  This comparator compares two numbers, A and B, on the input and produces two outputs, A=B and A>B.  (A and B are unsigned numbers throughout this exercise.)
   a) Find the minimal 2-level circuit implementation for these two functions.  First design a component using gates for this comparator using Active-HDL.  Then design the component using Verilog and continuous assignment. (Use different names for the two components.) Use the text fixture hw1a_tf.v to test your components.  Print your schematic, Verilog code and console output from the simulations.
   b) Now design two 8-bit comparators, one using schematics and one using structural Verilog, using four of your 2-bit comparators.  Use the test fixture hw1b_tf.v to test your components.  Print your schematic, Verilog code and console output from the simulations.