• Example serial port manipulation via Win32 APIs is now available
• UART and inverter test verilog. These are Active HDL archived projects, and you can either open them manually, or go to Design->Restore Design... and select the zip file. The invert_test design uses the invert design as a library.
  • UART inverter program
  • UART inverter test program
• Note on simulation - if you want to create a verilog test file, as I did for the UART/inverter, you have two options. You can create a new project, and import all the files (you don't need to copy them, just include them). You can also include the library from the design you want to test. Refer to Handling Libraries in VHDL, Verilog, and EDIF in the Active HDL online help for more details. Not that you will need to go into the Library Manager (View->Library Manager) and make the library associated with your design Global.
• 3.3v Cypress 128K x 8 Static RAM (CY7C1019CV33)
• SRAM verilog model to validate your access code
• Using Active HDL to program FPGA
• R-2R Ladder DAC diagram
• Relevant pinout. AJ-AN are connected to headers for your use.
• DS275 Line-Powered RS-232 Transceiver Chip
• VGA timing information
• VGA Pintout
• XCV1000 datasheet
  

  Device	System Gates	CLB Array	Logic Cells	Maximum Available I/O	Block RAM Bits	Maximum SelectRAM+ Bits
  XCV1000	1,124,022	64x96	27,648	512	131,072	393,216

• LED flashing program for XCV1000
• Active HDL TUTORIAL #1 . CREATING AND SIMULATING SIMPLE SCHEMATICS
• Active HDL TUTORIAL #2 . HIERARCHY, BUSSES AND TEST FIXTURES