OSCILLOSCOPE DEMONSTRATION

TECHNICAL NOTES

1. The Demonstration implements (on the XESS XSV-300 FPGA Development Board) a simple Oscilloscope.

2. Input is through the XSV’s audio input with a single channel output displayed via the XSV’s VGA output. The output is selectable between either the ‘left’ or ‘right’ stereo audio inputs using DIPSW8 (OFF = ‘left’, ON = ‘right’) with the selected channel displayed on the 7-segment displays.

3. The design does not contain any input triggering or provision for horizontal or vertical scale adjustment, however the vertical display is offset to the center of the display. Note that the inputs are AC-coupled (by default of the XSV Board’s design), with a 256-line full-scale display range of approximately 1.3 V_p-p.

4. VGA resolution is 640 pixels x 480 lines with standard VGA timing giving a display refresh rate of approximately 60 Hz. There is no interpolation between display points.

5. The display color is not used to impart any information, thus the XSV’s RAMDAC (provides more than 64 colors) is not required - board shunts J5, 6 and 7 should all be set to the 2-3 position. However, the display color is manually selectable using DIPSW1 through DIPSW6 as follows:

DIPSW1 Red LSB 0

DIPSW2 Red MSB 1

DIPSW3 Green LSB 0

DIPSW4 Green MSB 1

DIPSW5 Blue LSB 0

DIPSW6 Blue MSB 1

6. DIPSW status is reported on the XSV’s Bargraph (DIPSW7 is unused).

7. The design assumes an XSV Board Clock frequency of 25 MHz.

Christopher J. MORGAN

February 19, 2002