module pportctl(clk, pwe, pre, pds, bus, reset, aw, addr,pbsy);
input clk, pwe, pre, reset, pds;
input [6:0] bus;
output aw,pbsy;
output [6:0] addr;

reg waitReq;
reg firstByte;
reg [6:0] addr,size;
wire writeOK, readOK;

// combinational outputs
assign writeOK = waitReq & pds & pwe;
assign readOK = !waitReq & !pds & pre;
assign aw = writeOK;
assign pbsy = !waitReq;

// byte protocol
always @(posedge clk) begin
  if (reset) begin
     waitReq <= 1;
  end else begin
     if (waitReq & pds) 
       waitReq <= 0;
     if (!waitReq & !pds) 
       waitReq <= 1;
  end
end

// array protocol
always @(posedge clk) begin
   if (reset) begin 
      firstByte <= 1;
      addr <= 0;
      size <= 0;
   end if (readOK | writeOK) begin    // data is on the bus
         addr <= addr + 1;
         if (firstByte) begin 
            size <= bus; // size is on the bus
            firstByte <= 0;
         end else
            if (addr == size) begin 
              addr <= 0;
              firstByte <= 1;
         end
   end
end

endmodule