module PC();

reg clk, pds, pwe, reset, pre;
wire pbsy;
reg [7:0] data;
integer size, i;
wire [6:0] addr;
reg [7:0] mem [127:0];
wire [7:0] bus;
wire aw;

assign bus = pre ? mem[addr] : 8'bZ;
assign bus = pwe ? data : 8'bZ;

always @(posedge clk) begin
  if (aw) 
    mem[addr] = bus;
end

// instantiate the controller
pportctl hw(clk, pwe, pre, pds, bus[6:0], reset, aw, addr, pbsy);

// initialize inputs
initial begin clk = 0; pds = 0; pwe = 0; pre = 0; size = 20; end
// reset sequence
initial begin reset = 1; #25 reset = 0; end
// clock process
always #10 clk = ~clk;

//pretend to be the PC
initial begin 
  #35;
  // write data
  for (i = 0; i <= size; i=i+1) begin
    while (pbsy === 1) #1;
    data = i ? ~i : size;
    pwe = 1;
    pre = 0;
    #3 pds = 1;
    while (pbsy !== 1) #1;
    pds = 0;
  end
  // read it out
  for (i = 0; i <= size; i=i+1) begin
    while (pbsy === 1) #1;
    pwe = 0; 
    pre = 1;
    #3 pds = 1;
    while (pbsy !== 1) #1;
    pds = 0;
  end
  // read it out again
  for (i = 0; i <= size; i=i+1) begin
    while (pbsy === 1) #1;
    pwe = 0; 
    pre = 1;
    #3 pds = 1;
    while (pbsy !== 1) #1;
    pds = 0;
  end
  $finish;
end

endmodule