Day

Day	Lecture	Lab (by week) Supporting Docs	Homework assignment. Due on the day listed
M	---no class---
W 1/3	Review of Combinational Logic
F 1/5	Lab Intro, State Machine Review, HW1 Solutions		Design "BITS" using lookup tables in two ways: 2-levels with less than 300 bits, and any number of levels with less than 200 bits.
M 1/8	Dynamic Power (Clock), Gate Level Timing Model, Timing Diagram, Asynchronous Counter Problem,
W 1/10	State Machine Partitioning, Functional Timing Diagram, Asynchronous Counter Continued, Event Based State Diagram	Parallel Port Controller due 1/17 in class
F 1/12	Synchronous Design Rules, Synchronous Timing		Show the event based state machine diagram for the D flip flop, showing the effect of all events on all inputs for each state. Inputs are D, CLK, output is Q. Due 1/12
M 1/15	---no class---
W 1/17	Quiz 1 (30 Minutes)	Parallel Port I/O in Hardware w/ PC Software: Lab2	Clock Skew Problem
F 1/19	Quiz Review / What is a state machine
M 1/22	Clock Skew
W 1/24	System I/O Timing/ Verilog	Compression Problem from Lame: Lab3	Quiz problem 2 with Timing
F 1/26	Verilog		16bit pportctl, in Verilog
M 1/29	Design Process/ Verilog Library Example
W 1/31	Lame (MP3 Encoder) Overview
F 2/2	Quiz
M 2/5	Timing and Top-Down Design Process	Due Date for Lab3
W 2/7	Pipelining, Retiming		Lame Analysis
F 2/9	Pipelining, Temporal Logic
M 2/12	Floating Point Multiply Pipeline, Pipelining (Register duplication, c-slowing)		Pipelining for the pattern matcher (Correlator)
W 2/14	Convolution and applications in DSP	DSP algorithm form Lame : Lab4
F 2/16	Video Game Architecture VGA Interface Spec
M 2/19	---NO CLASS-----
W 2/21	Double Buffering	Due Date for Lab4	Modify the test pattern schematic (hand drawn okay) to provide X, Y relative to 0, 0 in the visible (non-blanked) part of the image. And...finish the schematic to implement double buffering. The Xilinx archive file has the schematic if you didn't get the handout in class. Also check out the VGA overview handout for the timing requirements
F 2/23	Latch Based Design
M 2/26	Latch Based Design		Latch based parity generator pipeline
W 2/28	Quiz	XSV300 Video and Audio Project Archives
F 3/3	Latches again, Quiz Review		Shuffle Exchange Sequencer Design
M 3/5	Exam/HW Review
W 3/7	----Canceled-------
F 3/9	Demo In Lab -- 327
M
Th 3/15	Final