Sequential Verilog
Sequential circuits are registers along with combinational logic
We will use only positive edge-triggered registers
- Latches and negative edge-trieggered registers can be used in restricted situations
Register is synthesized when assignment is triggered by “posedge clk”
module dreg (clk, d, q); input clk, d; output q; reg q;
always @(posedge clk) q = d;