HDLs

1/19/00


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Table of Contents

HDLs

Verilog/VHDL

Verilog

Verilog Introduction

Structural Model

Structural Model

Simple Behavioral Model

Verilog Data Types and Values

Verilog Numbers

Verilog Operators

Verilog Variables

Verilog Module

Verilog Continuous Assignment

Comparator Example

Comparator Example

Simple Behavioral Model - the always block

always Block

“Complete” Assignments

Imcomplete Triggers

Verilog if

Verilog if

Verilog case

Verilog case

Verilog case (cont)

Parallel Case

Verilog casex

casex Example

Verilog for

Another Behavioral Example

Verilog while/repeat/forever

full-case and parallel-case

Sequential Verilog

8-bit Register with Synchronous Reset

N-bit Register with Asynchronous Reset

Shift Register Example

Blocking and Non-Blocking Assignments

Swap (continued)

Non-Blocking Assignment

Counter Example

Finite State Machines

Verilog FSM - Reduce 1s example

Moore Verilog FSM (cont’d)

Mealy Verilog FSM for Reduce-1s example

Restricted FSM Implementation Style

Single-always Moore Machine (Not Recommended!)

Single-always Moore Machine (Not Recommended!)

Author: LIS

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