Design of Universal Shift Register

Nth cell

s0 and s1control mux

D

Q

CLK

CLEAR

Q[N-1](left)

Q[N+1](right)

Input[N]

to N-1th cell

to N+1th cell

clear s0 s1 new value 1 – – 0 0 0 0 output 0 0 1 output value of FF to left (shift right) 0 1 0 output value of FF to right (shift left) 0 1 1 input

• Consider one of the four flip-flops

  • new value at next clock cycle:

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