Pipelining
Delay, d, of slowest combinational stage determines performance
Throughput = 1/d : rate at which outputs are produced
Latency = n•d : number of stages * clock period
Pipelining increases circuit utilization
Registers slow down data, synchronize data paths
Wave-pipelining
- no pipeline registers - waves of data flow through circuit
- relies on equal-delay circuit paths - no short paths