Design Problem #7 (due Monday, Jan 24)
For this problem, you will use the Xilinx tools to modify and simulate the FIFO we designed in class
Restore a copy of the FIFO design from:
- ifilesrv1\courses\cse467\Winter00\HW7\
Simulate it using the fifotest script; make sure you understand it
Modify the design so that
- it will not execute a WRITE when it is FULL
- it will not execute a READ when empty
Modify the test script to test this new functionality
Hand in:
- The new schematic
- The new test script
- The simulation waveform output (one page please!)
- Circle the part of the waveform where the test tries to break the FIFO