Xilinx CAD Tools
Verilog (or VHDL) use to specify logic at a high-level
- combine with schematics, library components
Synopsys
- compiles Verilog to logic
- maps logic to the FPGA cells
- optimizes logic
Xilinx APR - automatic place and route (simulated annealing)
- provides controllability through constraints
- handles global signals
Xilinx Xdelay - measure delay properties of mapping and aid in iteration
Xilinx XACT - design editor to view final mapping results