Xilinx FPGA Combinational Logic Examples

• Key: General functions are limited to 5 inputs

  • (4 even better - 1/2 CLB)
  • No limitation on function complexity

• Example

  • 2-bit comparator: A B = C D and A B > C D implemented with 1 CLB  (GT) F = A C' + A B D' + B C' D' (EQ) G = A' B' C' D' + A' B C' D  + A B' C D' + A B C D

• Can implement some functions of > 5 inputs

• Examples:

  • 9-input parity generator implemented with 1 CLB 

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