Tradeoffs in FPGAs
Logic block - how are functions implemented: fixed functions (manipulate inputs) or programmable?
- support complex functions, need fewer blocks, but they are bigger so less of them on chip
- support simple functions, need more blocks, but they are smaller so more of them on chip
Interconnect
- how are logic blocks arranged?
- how many wires will be needed between them?
- are wires evenly distributed across chip?
- programmability slows wires down – are some wires specialized to long distances?
- how many inputs/outputs must be routed to/from each logic block?
- what utilization are we willing to accept? 50%? 20%? 90%?