Homework 1

Read Atmel Flash Microcontroller Architecture Overview. Answer the following questions:

1. If your program requires 150 bytes of data storage (not counting SFRs), how much RAM space is left for the stack? There are several possible answers to this question depending on what you include the 150 bytes above, so just be clear on your reasoning. To what value would you initialize the stack pointer, given your argument?

Most assumed that registered are not included in that number, probably a good assumption since you will want to use those for working memory. However, we probably would want to count the bit addressable space in the 150. We should also plan to put the data as low as possible in the RAM space since then we can access it either directly or indirectly. So start the stack area at 32+150 = 182. Since the SP gets incremented before the data is stored, we should initialize the SP to 181, or  B5H.

Common errors: counting the SFR (upper 128 direct) space as available for stack. It can't be used for stack since it can only be accessed through direct addressing mode.

Other approaches: initializing the stack to 20H (32) and placing data in the upper region of RAM. Doable, but probably not best practice. One person suggested that stack overflow would clobber program data, so better to put the stack above data. This is true, but it might be just as bad for the stack to overflow in upper memory. 

1. How does the register bank architecture serve to reduce code space as suggested by the document?  How can the register banks be used to improve the performance of subroutine calls and task switching? and what would the Compiler or OS, respectively, have to do to take advantage of them?

Most of you correctly concluded that using a 3 bit address for registers saves an extra instruction byte. However, only one person had the correct reasoning: that 5 bits are required to provide enough register access opcodes, leaving only 3 for register ID.  The choice of having 4 banks instead of, say, 8 is purely an architectural choice.

Common errors: Thinking that somehow, register access is faster than accessing other RAM locations. Actually all RAM locations, indirect or direct, take the same amount of time. The register instructions are provided for code compression, and the banking is provided for execution speed optimization.

Why banking?  most of you got this...to allow context switching to take place without saving all of the registers to the stack. The compiler just needs to insert code to change the PSW bank select bits prior to the subroutine jump, then change them back on return. Same with the OS in the case of context switching. Since there are only four banks, there is definitely a limit to how much this can be used. This is also important for reducing interrupt latency, something we will discuss later.

1. Give one or two probable reasons that the INC DPTR instruction requires twice as much time to execute as INC A?

Assuming that the CPU has only and 8 bit datapath, it is reasonable to conclude that two passes through the ALU are required to compute the 16 bit increment result. It could also be due to the fact that two accesses to memory are required as well. A final reason may be that this timing is maintained to provide timing compatibility across all 8051 implementations.

Other common errors

Failure to distinguish between code memory space and data memory space. The 8051 memory architecture has several memory spaces including: register, bit addressable, code, data, and external data (xdata). Instructions can only be executed out of code space which is ROM. The rest of the spaces are RAM. It is possble to combine xdata with the code space externally.