In this project, you will engage in the metacognitive skill of taking Cornell notes in a class besides CSE 390B and reflect on the practice of taking notes using a higher order of thinking. continue to engage metacognitively in your time-management as a student.
The technical part of this project consists of implementing memory modules that scale up in size and build the Program Counter (PC) of the CPU.
Navigate to the Project 4 assignment on Canvas. Download the document template
titled Project 4.docx. Open the document, read the instructions on the first page, and estimate the
amount of time you think it will take you to complete this project. Then, complete parts I, II, and III of the
project.
For this part of the project, take notes using the Cornell Note-taking method in any lecture from a class you are enrolled in this quarter. Throughout the lecture, take notes as you typically would in capturing the material discussed in class, but leave a 2.5" margin from the left of your document for questions. Following the conclusion of your class, create questions based on the notes that you had taken from class. Think of questions that may be asked of you for an upcoming assignment or exam, that strengthen your memory or understanding of the material or highlight connections between different parts of the class. At the bottom of your notes, summarize, in your own words, the key takeaways that were discussed in lecture. Once you have completed the Cornell Notes, submit a copy of the Cornell Notes you took and answer the following reflection questions:
The computer's main memory, also called Random Access Memory, or RAM, is an addressable sequence of n-bit registers, each designed to hold an n-bit value. In this project you will gradually build a RAM unit. This involves two main issues: (i) how to use gate logic to store bits persistently, over time, and (ii) how to use gate logic to locate ("address") the memory register on which we wish to operate.
To complete this assignment, you will need to use git to access the starter materials that have been pushed to
your repository by the course staff.
First, run git status and see if it reports any changes. If you have any, you'll need to commit them
before proceeding (git add . followed by git commit -m "Your message here").
Then, run:
git pull (Downloads commits on the GitLab server to your local repository)
After running this command, you have synchronized the local copy of your repository with the copy on the server.
In this project, you will again build a set of chips. The only building blocks you can use are "primitives"
(Nand,
the "combinational primitive", and DFF, the "sequential primitive") as well as any previous chips
(whether in previous projects or in this project). Remember that previous projects list
"additional chips" you did not implement but are allowed to use! As before, we highly recommend you implement in
the order listed here.
| Chip Name | Description | Test Script | Expected Output |
|---|---|---|---|
| DFF | Data Flip-Flop (primitive) | ||
| Bit | 1-bit register | Bit.tst | Bit.cmp |
| Register | 16-bit register | Register.tst | Register.cmp |
| RAM8 | 16-bit, 8-register memory | RAM8.tst | RAM8.cmp |
| RAM64 | 16-bit, 64-register memory | RAM64.tst | RAM64.cmp |
| RAM512 | 16-bit, 512-register memory | RAM512.tst | RAM512.cmp |
| RAM4K | 16-bit, 4096-register memory | RAM4K.tst | RAM4K.cmp |
| RAM16K | 16-bit, 16384-register memory | RAM16K.tst | RAM16K.cmp |
| PC | 16-bit program counter | PC.tst | PC.cmp |
When loaded into the supplied Hardware Simulator, your chip design (modified .hdl program), tested on
the supplied
.tst script, should produce the outputs listed in the supplied .cmp file. If that is not
the case, the simulator
will let you know.
You will find Chapter 3 helpful for this project. More details about sequential logic in HDL can be found in Appendix A. Since you will be depending heavily on chips from Projects 2 and 3, you may find this Chip Set Overview helpful to look up the chip signature (i.e., names of connections) for the chips you need. Like the previous projects, you may also find this HDL Survival Guide written by Mark Armbrust helpful.
The DFF gate is considered primitive, so you do not have to implement it. When the simulator
encounters it in
other chips, the built-in version will be used.
RAM memory usage: When building progressively larger versions of RAM, your implementation will require the
hardware simulator to process an enormous number of recursive underlying chips.
In order to avoid running out of memory (and significantly speed up the simulation), we've partitioned this
project into two folders: "normal" and "large". This way, when you implement the "large" RAM chips in their own
folder, they will use
the built-in implementations of the smaller RAM chips, which are much more optimized. Note: The folder division is
for efficiency purposes only and has no deeper meaning beyond that.
After implementing the "large" RAM chips, you will return to the "normal" folder to implement PC.hdl.
To submit Part II, make sure you commit and push your changes, then tag them as project-4 and push
that tag as well:
git add . (Stage all your changes)git commit -m "Finish project 4" (Bundle those changes as a commit)git push (Push that commit to the GitLab server)git tag project-4 (Add the project-4 tag to that last commit)git push --tags (Push the tag to the GitLab server)Lastly, verify that the tag and all your code is uploaded correctly by checking on https://gitlab.cs.washington.edu/ .
In the document Project 4.docx, record how long the project took you in reality and write a short
written reflection about your experience completing this project.
Make sure you have submitted your completed .hdl files on GitLab by following the instructions in
the heading above titled "Submitting Part II." Then, save your changes from the Project 4.docx
document as a PDF and
submit the document to the assignment titled "Project 4: Cornell Note-taking & Building Memory" on Gradescope. Project 4 will be considered completed once you
have followed these steps.