• Do the following problems, and hand in the answers by the start of class on Wednesday, May 19.

The purpose of these problems is to make sure you really understand the concepts of pipelining, dependences and hazards, the implementation of hazard detection and resolution, and the ramification of pipelining and hazards on performance.

1. Problem 6.9

Fill out what you can from the information taken from the sources suggested in the problem. Put question marks in the instruction opcode and operand fields that you can't determine.


2. Problem 6.12
3. Problem 6.14
4. Problem 6.19
5. Problem 6.20
6. Problem 6.26
7. Problem 6.31
   
   
8. Assume that memory accesses have become the critical path in the implementation of our architecture, so we have deepened the pipeline from 5 stages to 7:

IF1 IF2 ID EX MEM1 MEM2 WB

Which stages' outputs may need to be forwarded back to which other inputs?  What is the maximum number of stages "back" we will need to forward data (i.e. to the previous stage, 2 stages earlier, etc.)?

Redraw Figure 6.36 (using the instructions provided in the figure) to reflect the execution of these instructions under the new pipeline structure.  Show all cycles until the instruction sequence completes.