CSE 378 - Tentative and Developing Course Outline

Last modified on 04/13/99

WeekMondayWednesdayFriday
3/29 Administration
Architecture overview
read Chapter 1.2; the rest of the chapter
is an optional overview of computers
What is architecture?
Binary number system
Chapter 4.1-4.3
Overview of MIPS ISA
Computation instructions
Chapter 3.1-3.4, Appendix A.1-A.4

4/5 Data transfer & control instructions
Chapter 3.5
Binary number system assignment due
Other instructions
Addressing modes
Chapter 3.8

Procedure calls
Chapter 3.6, Appendix A.6

4/12 Evolution of ISAs
Chapter 3.15
Instruction set assignment due
Comparing RISC & CISC
Performance Metrics
Chapter 2 & pp. 99-101
4/19 TA lecture
Single-cycle implementation: Datapath
Chapter 5, sections 1 and 2 (see assignment 3 for the parts you should omit)
Single-cycle implementation: Control
Chapter 5, section 3
First JVM assignment due
Multiple cycle implementation
Chapter 5, section 4
4/26 Microprogramming
Chapter 5, sections 5, 7 - 10
Microprogramming
Review for midterm
Performance & datapath assignment due
TA lecture
Pipelining
Chapter 6, sections 1 - 3
5/3 Midterm
Pipelining
Structural hazards
Data hazards
Chapter 6, sections 4 & 5
5/10 Control hazards
Pipelines in today's microprocessors
Chapter 6, sections 8 on
Second JVM assignment due
Pipelines in today's microprocessors
5/17 Pipelines in today's microprocessors
Introduction to memory hierarchies
Chapter 7, section 1
Caches
Pipelining assignment due
Cache design
Chapter 7, sections 2 & 3 & pp. 609-611, 629
5/24 Cache design
Cache performance
Cache design & performance
Chapter 7, sections 4 & 5
Memory hierarchy assignment due
Virtual Memory
Chapter 7, sections 6-9
5/31 Memorial day Virtual Memory
Exception handling
Review for the final
P. 223, Sections 5.6, 6.7
Cache simulator due
6/7 No class
Final Exam 8:30

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