For this assignment, you will be using SPIM and MIPS assembly language to write a simple trace-driven simulator for assessing cache performance. Trace-driven simulation is commonly used to assess performance of memory hierarchy designs.
A general simulator works as follows.
Given:
Process each memory reference, decomposing it into tag, index, and offset components. Check if the reference hits in the appropriate cache (note that the simulator does not actually bring data in or out of its simulated cache; rather, it pretends that it has the data there). Take the appropriate action (change valid/dirty bits, replace blocks, etc.) and record the statistics.
The output will be a set of statistics, including read hit ratio, write hit ratio, average memory access time, and so forth.
Your assignment will simulate a D-cache only, and will do the following:
Given as Input:
You will output to the SPIM console:
For the purposes of debugging, you are encouraged to test your program on smaller cache sizes and smaller input traces first.