IF1 IF2 ID EX MEM1 MEM2 WB
Which stages' outputs may need to be forwarded back to which other inputs? What is the maximum number of stages "back" we will need to forward data (i.e. to the previous stage, 2 stages earlier, etc.)?
Redraw Figure 6.36 (using the instructions provided in the figure) to reflect the execution of this instructions under the new pipeline structure. Show all cycles until the instruction sequence completes.