CSE 378 - Tentative and Developing Course Outline

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3/30 Administration
Architecture overview
read Chapter 1		 What is architecture?
Binary number system
Chapter 4.1-4.3		 Overview of MIPS ISA
Computation instructions
Chapter 3, Appendix A
4/6 Data transfer & control instructions
 Other instructions
Addressing modes
Binary number system assignment due		 Procedure calls

4/13 Evolution of ISAs
 Comparing RISC & CISC
Chapter 2
Instruction set assignment due		 Performance Metrics
4/20 Single-cycle implementation: Datapath
Chapter 5, sections 1 and 2
 Single-cycle implementation: Control
Chapter 5, section 3
First JVM assignment due		 Single-cycle implementation
4/27 Multicycle implementation:datapath
Chapter 5, section 4
 Multicycle implementation:control
Datapath & performance assignment due
 Microprogramming
Review for midterm Chapter 5, sections 5, 7 - 10
5/4 Midterm
 Pipelining
Chapter 6, sections 1 - 3		 Data hazards
Chapter 6, sections 4 & 5
5/11 Data hazards
Second JVM assignment due
Control hazards
Chapter 6, sections 8 on
Pipelines in today's microprocessors
5/18 Pipelines in today's microprocessors
pipelining assignment due		 Introduction to memory hierarchies
Chapter 7, section 1
 Caches and cache design
Chapter 7, sections 2 & 3 & p. 629
5/25 Memorial day Cache design & performance
Virtual Memory
Chapter 7, section 4
memory hierarchy assignment due		 Virtual Memory
Chapter 7, section 5
6/1 Wrapup on the memory system
Chapter 7, sections 6-9		 Exception handling
I/O
Chapter 8, sections 3-5		 Review for the final
I/O
cache simulator due
6/8 No class
 Final Exam 8:30

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