`timescale 1 ns / 1 ps

module HazardDetectionUnit( 
	input wire ID_Branch,
	input wire ID_JR,
	input wire [25:16] ID_Inst, /* rs and rt fields of instruction in ID */
	input wire EX_Load,
	input wire MEM_Load,
	input wire [4:0] EX_WriteReg,
	input wire EX_RegWrite,
	input wire [4:0] MEM_WriteReg,
	input wire MEM_RegWrite,
	output wire LoadEnable,
	output wire IDEXReg_Clear);
		
	wire branch_hazard;
	wire load_hazard; 
		
	assign LoadEnable = ~( branch_hazard | load_hazard );
	assign IDEXReg_Clear =  branch_hazard | load_hazard ;
endmodule