`timescale 1 ns / 1 ps

module ForwardingUnit( 
	input wire [4:0] MEM_WriteReg, /* Index of destination register for instruction in MEM */
	input wire MEM_RegWrite,       /* Whether instruction in MEM actually update Regfile */
	input wire [4:0] WB_WriteReg,  /* Index of destination register for instruction in WB */
	input wire WB_RegWrite,		   /* Whether instruction in WB actually updates Regfile */
	input wire [25:16] ID_Inst,    /* rs, rt field of ID_Inst */
	input wire [25:16] EX_Inst,    /* rs, rt field of EX_Inst */
	input wire ID_Branch,			   /* is ID_Inst a branch instruction? */
	input wire ID_JR,				   /* is ID_Inst JR or JALR? */
	input wire EX_JAL,				   /* is EX_Inst JAL or JALR? */
	output wire [1:0] Fwd_EX_RS, /* forwarding signal to use in EX Stage */
	output wire [1:0] Fwd_EX_RT, /* forwarding signal to use in EX Stage */
	output wire Fwd_ID_RS, 	/* forwarding signal to use in ID Stage */
	output wire Fwd_ID_RT   /* forwarding signal to use in ID Stage */
	);
		
	// Insert your logic here.
	
	localparam NO_FORWARD = 2'b00;
	localparam JAL_ADDRESS_COMPUTE = 2'b01;
	localparam FORWARD_FROM_MEM = 2'b10;
	localparam FORWARD_FROM_WB = 2'b11;

	//// Check for RegWrite to a non-$zero register
	wire mem_write_nonzero_reg, wb_write_nonzero_reg;
	
	//// Check for dependence between MEM and EX ( set Fwd_EX_R* to FORWARD_FROM_MEM ) 
	wire ex_mem_rs_match;
	wire ex_mem_rt_match;
	//// Check for dependence between WB and EX ( set Fwd_EX_R* to FORWARD_FROM_WB ) 
	wire ex_wb_rs_match;
	wire ex_wb_rt_match;
	
	//// Check for dependence between MEM and ID ( set Fwd_ID_RS for branches, JR, JALR )
	wire id_mem_rs_match;
	//// Check for dependence between MEM and ID ( set Fwd_ID_RT for branches )
	wire id_mem_rt_match;
	
	assign Fwd_EX_RS = NO_FORWARD;

	assign Fwd_EX_RT = NO_FORWARD;
		
	assign Fwd_ID_RS = 1'b0;
	assign Fwd_ID_RT = 1'b0;
	
endmodule