//----------------------------------------------------------------------------- // // Title : phase1_tf // Design : lab3 // Author : Steven // Company : University of Washington CSE // //----------------------------------------------------------------------------- // // File : phase1_tf.v // Generated : Mon Oct 30 15:07:43 2006 // From : E:\my_designs\AndrewH\lab3\src\Tests\phase1_tf_settings.txt // By : tb_verilog.pl ver. ver 1.2s // //----------------------------------------------------------------------------- // // Description : // //----------------------------------------------------------------------------- `timescale 1ps / 1ps module phase1_tf; //Internal signals declarations: wire Store_actual; reg Store; wire SignedLoad_actual; reg SignedLoad; reg [31:0]Inst; wire [31:0]PCOut_actual; reg [31:0]PCOut; reg [31:0]CPUDataIn; wire [1:0]MemSize_actual; reg [1:0]MemSize; wire [31:0]CPUDataOut_actual; reg [31:0]CPUDataOut; wire [31:0]ALUOut_actual; reg [31:0]ALUOut; reg RESET; reg CLK; wire [31:0]ID_Inst_actual; reg [31:0]ID_Inst; wire [31:0]EX_Inst_actual; reg [31:0]EX_Inst; wire [31:0]MEM_Inst_actual; reg [31:0]MEM_Inst; wire [31:0]WB_Inst_actual; reg [31:0]WB_Inst; wire EX_RegWrite_actual; reg EX_RegWrite; wire MEM_RegWrite_actual; reg MEM_RegWrite; wire WB_RegWrite_actual; reg WB_RegWrite; wire [4:0]EX_WriteReg_actual; reg [4:0]EX_WriteReg; wire [4:0]MEM_WriteReg_actual; reg [4:0]MEM_WriteReg; wire [4:0]WB_WriteReg_actual; reg [4:0]WB_WriteReg; wire [31:0]WB_CPUDataIn_actual; reg [31:0]WB_CPUDataIn; wire [31:0]MEM_CPUDataOut_actual; reg [31:0]MEM_CPUDataOut; wire [31:0]MEM_ALUOut_actual; reg [31:0]MEM_ALUOut; wire [31:0]WB_ALUOut_actual; reg [31:0]WB_ALUOut; wire [31:0]Reg1_actual; reg [31:0]Reg1; wire [31:0]Reg2_actual; reg [31:0]Reg2; wire [31:0]Reg3_actual; reg [31:0]Reg3; wire [31:0]Reg4_actual; reg [31:0]Reg4; wire [31:0]Reg5_actual; reg [31:0]Reg5; wire [31:0]Reg6_actual; reg [31:0]Reg6; wire [31:0]Reg7_actual; reg [31:0]Reg7; wire [31:0]Reg8_actual; reg [31:0]Reg8; wire [31:0]Reg9_actual; reg [31:0]Reg9; wire [31:0]Reg10_actual; reg [31:0]Reg10; wire [31:0]Reg11_actual; reg [31:0]Reg11; wire [31:0]Reg12_actual; reg [31:0]Reg12; wire [31:0]Reg13_actual; reg [31:0]Reg13; wire [31:0]Reg14_actual; reg [31:0]Reg14; wire [31:0]Reg15_actual; reg [31:0]Reg15; wire [31:0]Reg16_actual; reg [31:0]Reg16; wire [31:0]Reg17_actual; reg [31:0]Reg17; wire [31:0]Reg18_actual; reg [31:0]Reg18; wire [31:0]Reg19_actual; reg [31:0]Reg19; wire [31:0]Reg20_actual; reg [31:0]Reg20; wire [31:0]Reg21_actual; reg [31:0]Reg21; wire [31:0]Reg22_actual; reg [31:0]Reg22; wire [31:0]Reg23_actual; reg [31:0]Reg23; wire [31:0]Reg24_actual; reg [31:0]Reg24; wire [31:0]Reg25_actual; reg [31:0]Reg25; wire [31:0]Reg26_actual; reg [31:0]Reg26; wire [31:0]Reg27_actual; reg [31:0]Reg27; wire [31:0]Reg28_actual; reg [31:0]Reg28; wire [31:0]Reg29_actual; reg [31:0]Reg29; wire [31:0]Reg30_actual; reg [31:0]Reg30; wire [31:0]Reg31_actual; reg [31:0]Reg31; //LOG file declaration. integer report_file; //Wait time declaration used in ports monitoring. //One parameter is declared for every port. parameter Default_wait_time = 10; parameter Store_WaitTime = Default_wait_time;//WaitTime Parameter for port Store parameter SignedLoad_WaitTime = Default_wait_time;//WaitTime Parameter for port SignedLoad parameter PCOut_WaitTime = Default_wait_time;//WaitTime Parameter for port PCOut parameter MemSize_WaitTime = Default_wait_time;//WaitTime Parameter for port MemSize parameter CPUDataOut_WaitTime = Default_wait_time;//WaitTime Parameter for port CPUDataOut parameter ALUOut_WaitTime = Default_wait_time;//WaitTime Parameter for port ALUOut parameter ID_Inst_WaitTime = Default_wait_time;//WaitTime Parameter for port ID_Inst parameter EX_Inst_WaitTime = Default_wait_time;//WaitTime Parameter for port EX_Inst parameter MEM_Inst_WaitTime = Default_wait_time;//WaitTime Parameter for port MEM_Inst parameter WB_Inst_WaitTime = Default_wait_time;//WaitTime Parameter for port WB_Inst parameter EX_RegWrite_WaitTime = Default_wait_time;//WaitTime Parameter for port EX_RegWrite parameter MEM_RegWrite_WaitTime = Default_wait_time;//WaitTime Parameter for port MEM_RegWrite parameter WB_RegWrite_WaitTime = Default_wait_time;//WaitTime Parameter for port WB_RegWrite parameter EX_WriteReg_WaitTime = Default_wait_time;//WaitTime Parameter for port EX_WriteReg parameter MEM_WriteReg_WaitTime = Default_wait_time;//WaitTime Parameter for port MEM_WriteReg parameter WB_WriteReg_WaitTime = Default_wait_time;//WaitTime Parameter for port WB_WriteReg parameter WB_CPUDataIn_WaitTime = Default_wait_time;//WaitTime Parameter for port WB_CPUDataIn parameter MEM_CPUDataOut_WaitTime = Default_wait_time;//WaitTime Parameter for port MEM_CPUDataOut parameter MEM_ALUOut_WaitTime = Default_wait_time;//WaitTime Parameter for port MEM_ALUOut parameter WB_ALUOut_WaitTime = Default_wait_time;//WaitTime Parameter for port WB_ALUOut parameter Reg1_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg1 parameter Reg2_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg2 parameter Reg3_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg3 parameter Reg4_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg4 parameter Reg5_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg5 parameter Reg6_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg6 parameter Reg7_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg7 parameter Reg8_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg8 parameter Reg9_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg9 parameter Reg10_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg10 parameter Reg11_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg11 parameter Reg12_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg12 parameter Reg13_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg13 parameter Reg14_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg14 parameter Reg15_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg15 parameter Reg16_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg16 parameter Reg17_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg17 parameter Reg18_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg18 parameter Reg19_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg19 parameter Reg20_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg20 parameter Reg21_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg21 parameter Reg22_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg22 parameter Reg23_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg23 parameter Reg24_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg24 parameter Reg25_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg25 parameter Reg26_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg26 parameter Reg27_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg27 parameter Reg28_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg28 parameter Reg29_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg29 parameter Reg30_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg30 parameter Reg31_WaitTime = Default_wait_time;//WaitTime Parameter for port Reg31 //Simulation time parameter SimulationTime = 64'd7530000 + Default_wait_time + 1; //Errors counter integer errors_counter; //Block of Comparison functions declarations. A separate function for each output port is defined. //Comparison function for port "Store" function compare_Store; input UUT_output; input PATTERN; begin if (UUT_output !== PATTERN) compare_Store = 1'b1; else compare_Store = 1'b0; end endfunction //Comparison function for port "SignedLoad" function compare_SignedLoad; input UUT_output; input PATTERN; begin if (UUT_output !== PATTERN) compare_SignedLoad = 1'b1; else compare_SignedLoad = 1'b0; end endfunction //Comparison function for port "PCOut" function compare_PCOut; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_PCOut = 1'b1; else compare_PCOut = 1'b0; end endfunction //Comparison function for port "MemSize" function compare_MemSize; input [1:0] UUT_output; input [1:0] PATTERN; begin if (UUT_output !== PATTERN) compare_MemSize = 1'b1; else compare_MemSize = 1'b0; end endfunction //Comparison function for port "CPUDataOut" function compare_CPUDataOut; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_CPUDataOut = 1'b1; else compare_CPUDataOut = 1'b0; end endfunction //Comparison function for port "ALUOut" function compare_ALUOut; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_ALUOut = 1'b1; else compare_ALUOut = 1'b0; end endfunction //Comparison function for port "ID_Inst" function compare_ID_Inst; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_ID_Inst = 1'b1; else compare_ID_Inst = 1'b0; end endfunction //Comparison function for port "EX_Inst" function compare_EX_Inst; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_EX_Inst = 1'b1; else compare_EX_Inst = 1'b0; end endfunction //Comparison function for port "MEM_Inst" function compare_MEM_Inst; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_MEM_Inst = 1'b1; else compare_MEM_Inst = 1'b0; end endfunction //Comparison function for port "WB_Inst" function compare_WB_Inst; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_WB_Inst = 1'b1; else compare_WB_Inst = 1'b0; end endfunction //Comparison function for port "EX_RegWrite" function compare_EX_RegWrite; input UUT_output; input PATTERN; begin if (UUT_output !== PATTERN) compare_EX_RegWrite = 1'b1; else compare_EX_RegWrite = 1'b0; end endfunction //Comparison function for port "MEM_RegWrite" function compare_MEM_RegWrite; input UUT_output; input PATTERN; begin if (UUT_output !== PATTERN) compare_MEM_RegWrite = 1'b1; else compare_MEM_RegWrite = 1'b0; end endfunction //Comparison function for port "WB_RegWrite" function compare_WB_RegWrite; input UUT_output; input PATTERN; begin if (UUT_output !== PATTERN) compare_WB_RegWrite = 1'b1; else compare_WB_RegWrite = 1'b0; end endfunction //Comparison function for port "EX_WriteReg" function compare_EX_WriteReg; input [4:0] UUT_output; input [4:0] PATTERN; begin if (UUT_output !== PATTERN) compare_EX_WriteReg = 1'b1; else compare_EX_WriteReg = 1'b0; end endfunction //Comparison function for port "MEM_WriteReg" function compare_MEM_WriteReg; input [4:0] UUT_output; input [4:0] PATTERN; begin if (UUT_output !== PATTERN) compare_MEM_WriteReg = 1'b1; else compare_MEM_WriteReg = 1'b0; end endfunction //Comparison function for port "WB_WriteReg" function compare_WB_WriteReg; input [4:0] UUT_output; input [4:0] PATTERN; begin if (UUT_output !== PATTERN) compare_WB_WriteReg = 1'b1; else compare_WB_WriteReg = 1'b0; end endfunction //Comparison function for port "WB_CPUDataIn" function compare_WB_CPUDataIn; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_WB_CPUDataIn = 1'b1; else compare_WB_CPUDataIn = 1'b0; end endfunction //Comparison function for port "MEM_CPUDataOut" function compare_MEM_CPUDataOut; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_MEM_CPUDataOut = 1'b1; else compare_MEM_CPUDataOut = 1'b0; end endfunction //Comparison function for port "MEM_ALUOut" function compare_MEM_ALUOut; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_MEM_ALUOut = 1'b1; else compare_MEM_ALUOut = 1'b0; end endfunction //Comparison function for port "WB_ALUOut" function compare_WB_ALUOut; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_WB_ALUOut = 1'b1; else compare_WB_ALUOut = 1'b0; end endfunction //Comparison function for port "Reg1" function compare_Reg1; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg1 = 1'b1; else compare_Reg1 = 1'b0; end endfunction //Comparison function for port "Reg2" function compare_Reg2; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg2 = 1'b1; else compare_Reg2 = 1'b0; end endfunction //Comparison function for port "Reg3" function compare_Reg3; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg3 = 1'b1; else compare_Reg3 = 1'b0; end endfunction //Comparison function for port "Reg4" function compare_Reg4; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg4 = 1'b1; else compare_Reg4 = 1'b0; end endfunction //Comparison function for port "Reg5" function compare_Reg5; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg5 = 1'b1; else compare_Reg5 = 1'b0; end endfunction //Comparison function for port "Reg6" function compare_Reg6; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg6 = 1'b1; else compare_Reg6 = 1'b0; end endfunction //Comparison function for port "Reg7" function compare_Reg7; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg7 = 1'b1; else compare_Reg7 = 1'b0; end endfunction //Comparison function for port "Reg8" function compare_Reg8; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg8 = 1'b1; else compare_Reg8 = 1'b0; end endfunction //Comparison function for port "Reg9" function compare_Reg9; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg9 = 1'b1; else compare_Reg9 = 1'b0; end endfunction //Comparison function for port "Reg10" function compare_Reg10; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg10 = 1'b1; else compare_Reg10 = 1'b0; end endfunction //Comparison function for port "Reg11" function compare_Reg11; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg11 = 1'b1; else compare_Reg11 = 1'b0; end endfunction //Comparison function for port "Reg12" function compare_Reg12; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg12 = 1'b1; else compare_Reg12 = 1'b0; end endfunction //Comparison function for port "Reg13" function compare_Reg13; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg13 = 1'b1; else compare_Reg13 = 1'b0; end endfunction //Comparison function for port "Reg14" function compare_Reg14; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg14 = 1'b1; else compare_Reg14 = 1'b0; end endfunction //Comparison function for port "Reg15" function compare_Reg15; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg15 = 1'b1; else compare_Reg15 = 1'b0; end endfunction //Comparison function for port "Reg16" function compare_Reg16; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg16 = 1'b1; else compare_Reg16 = 1'b0; end endfunction //Comparison function for port "Reg17" function compare_Reg17; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg17 = 1'b1; else compare_Reg17 = 1'b0; end endfunction //Comparison function for port "Reg18" function compare_Reg18; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg18 = 1'b1; else compare_Reg18 = 1'b0; end endfunction //Comparison function for port "Reg19" function compare_Reg19; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg19 = 1'b1; else compare_Reg19 = 1'b0; end endfunction //Comparison function for port "Reg20" function compare_Reg20; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg20 = 1'b1; else compare_Reg20 = 1'b0; end endfunction //Comparison function for port "Reg21" function compare_Reg21; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg21 = 1'b1; else compare_Reg21 = 1'b0; end endfunction //Comparison function for port "Reg22" function compare_Reg22; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg22 = 1'b1; else compare_Reg22 = 1'b0; end endfunction //Comparison function for port "Reg23" function compare_Reg23; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg23 = 1'b1; else compare_Reg23 = 1'b0; end endfunction //Comparison function for port "Reg24" function compare_Reg24; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg24 = 1'b1; else compare_Reg24 = 1'b0; end endfunction //Comparison function for port "Reg25" function compare_Reg25; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg25 = 1'b1; else compare_Reg25 = 1'b0; end endfunction //Comparison function for port "Reg26" function compare_Reg26; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg26 = 1'b1; else compare_Reg26 = 1'b0; end endfunction //Comparison function for port "Reg27" function compare_Reg27; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg27 = 1'b1; else compare_Reg27 = 1'b0; end endfunction //Comparison function for port "Reg28" function compare_Reg28; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg28 = 1'b1; else compare_Reg28 = 1'b0; end endfunction //Comparison function for port "Reg29" function compare_Reg29; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg29 = 1'b1; else compare_Reg29 = 1'b0; end endfunction //Comparison function for port "Reg30" function compare_Reg30; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg30 = 1'b1; else compare_Reg30 = 1'b0; end endfunction //Comparison function for port "Reg31" function compare_Reg31; input [31:0] UUT_output; input [31:0] PATTERN; begin if (UUT_output !== PATTERN) compare_Reg31 = 1'b1; else compare_Reg31 = 1'b0; end endfunction // Unit Under Test port map cpu_wrapper UUT ( .Store(Store_actual), .SignedLoad(SignedLoad_actual), .Inst(Inst), .PCOut(PCOut_actual), .CPUDataIn(CPUDataIn), .MemSize(MemSize_actual), .CPUDataOut(CPUDataOut_actual), .ALUOut(ALUOut_actual), .RESET(RESET), .CLK(CLK), .ID_Inst(ID_Inst_actual), .EX_Inst(EX_Inst_actual), .MEM_Inst(MEM_Inst_actual), .WB_Inst(WB_Inst_actual), .EX_RegWrite(EX_RegWrite_actual), .MEM_RegWrite(MEM_RegWrite_actual), .WB_RegWrite(WB_RegWrite_actual), .EX_WriteReg(EX_WriteReg_actual), .MEM_WriteReg(MEM_WriteReg_actual), .WB_WriteReg(WB_WriteReg_actual), .WB_CPUDataIn(WB_CPUDataIn_actual), .MEM_CPUDataOut(MEM_CPUDataOut_actual), .MEM_ALUOut(MEM_ALUOut_actual), .WB_ALUOut(WB_ALUOut_actual), .Reg1(Reg1_actual), .Reg2(Reg2_actual), .Reg3(Reg3_actual), .Reg4(Reg4_actual), .Reg5(Reg5_actual), .Reg6(Reg6_actual), .Reg7(Reg7_actual), .Reg8(Reg8_actual), .Reg9(Reg9_actual), .Reg10(Reg10_actual), .Reg11(Reg11_actual), .Reg12(Reg12_actual), .Reg13(Reg13_actual), .Reg14(Reg14_actual), .Reg15(Reg15_actual), .Reg16(Reg16_actual), .Reg17(Reg17_actual), .Reg18(Reg18_actual), .Reg19(Reg19_actual), .Reg20(Reg20_actual), .Reg21(Reg21_actual), .Reg22(Reg22_actual), .Reg23(Reg23_actual), .Reg24(Reg24_actual), .Reg25(Reg25_actual), .Reg26(Reg26_actual), .Reg27(Reg27_actual), .Reg28(Reg28_actual), .Reg29(Reg29_actual), .Reg30(Reg30_actual), .Reg31(Reg31_actual)); initial begin report_file=$fopen("$DSN\\src\\Tests\\phase1_report.log"); errors_counter = 0; #SimulationTime; if (errors_counter) begin $display("Errors were encountered, differences are listed in phase1_report.log"); $fdisplay(report_file,"Some vectors failed."); end else begin $display("All vectors passed."); $fdisplay(report_file,"All vectors passed."); end $fclose(report_file); $finish; end //Below code was generated based on waveform file: "E:\my_designs\AndrewH\lab3\compile\phase1.vhr" initial begin : STIMUL // begin of stimulus process #0 WB_Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; ID_Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; EX_Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; MEM_Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; MEM_RegWrite = 1'bx; EX_RegWrite = 1'bx; MEM_WriteReg = 5'bXXXXX; EX_WriteReg = 5'bXXXXX; WB_RegWrite = 1'bx; WB_WriteReg = 5'bXXXXX; WB_CPUDataIn = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; MEM_CPUDataOut = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; MEM_ALUOut = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; WB_ALUOut = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; SignedLoad = 1'bx; Store = 1'bx; Inst = 32'b00100000000000100000000000000001; PCOut = 32'b00000000000000000000000000000000; CPUDataIn = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; CPUDataOut = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; MemSize = 2'bXX; ALUOut = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; RESET = 1'b1; CLK = 1'b0; Reg1 = 32'b00000000000000000000000000000001; Reg2 = 32'b00000000000000000000000000000010; Reg3 = 32'b00000000000000000000000000000011; Reg4 = 32'b00000000000000000000000000000100; Reg5 = 32'b00000000000000000000000000000101; Reg6 = 32'b00000000000000000000000000000110; Reg7 = 32'b00000000000000000000000000000111; Reg8 = 32'b00000000000000000000000000001000; Reg9 = 32'b00000000000000000000000000001001; Reg10 = 32'b00000000000000000000000000001010; Reg11 = 32'b00000000000000000000000000001011; Reg12 = 32'b00000000000000000000000000001100; Reg13 = 32'b00000000000000000000000000001101; Reg14 = 32'b00000000000000000000000000001110; Reg15 = 32'b00000000000000000000000000001111; Reg16 = 32'b00000000000000000000000000010000; Reg17 = 32'b00000000000000000000000000010001; Reg18 = 32'b00000000000000000000000000010010; Reg20 = 32'b00000000000000000000000000010100; Reg19 = 32'b00000000000000000000000000010011; Reg21 = 32'b00000000000000000000000000010101; Reg22 = 32'b00000000000000000000000000010110; Reg23 = 32'b00000000000000000000000000010111; Reg24 = 32'b00000000000000000000000000011000; Reg25 = 32'b00000000000000000000000000011001; Reg26 = 32'b00000000000000000000000000011010; Reg27 = 32'b00000000000000000000000000011011; Reg28 = 32'b00000000000000000000000000011100; Reg29 = 32'b00000000000000000000000000011101; Reg31 = 32'b00000000000000000000000000011111; Reg30 = 32'b00000000000000000000000000011110; #330000; //0 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00000000000000000000000000000000; MEM_RegWrite = 1'b0; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b00000; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00000; WB_CPUDataIn = 32'b00000000000000000000000000000000; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000000; SignedLoad = 1'b0; Store = 1'b0; CPUDataIn = 32'b00000000000000000000000000000000; CPUDataOut = 32'b00000000000000000000000000000000; MemSize = 2'b00; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #10000; //330000 RESET = 1'b0; #10000; //340000 CLK = 1'b0; #20000; //350000 ID_Inst = 32'b00100000000000100000000000000001; EX_RegWrite = 1'b1; Inst = 32'b00100000000000111111111111111111; PCOut = 32'b00000000000000000000000000000100; CLK = 1'b1; #20000; //370000 CLK = 1'b0; #20000; //390000 ID_Inst = 32'b00100000000000111111111111111111; EX_Inst = 32'b00100000000000100000000000000001; MEM_RegWrite = 1'b1; EX_WriteReg = 5'b00010; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000000000001000; CLK = 1'b1; #20000; //410000 CLK = 1'b0; #20000; //430000 ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00100000000000111111111111111111; MEM_Inst = 32'b00100000000000100000000000000001; MEM_WriteReg = 5'b00010; EX_WriteReg = 5'b00011; WB_RegWrite = 1'b1; MEM_CPUDataOut = 32'b00000000000000000000000000000010; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000000010000000100000; PCOut = 32'b00000000000000000000000000001100; CPUDataOut = 32'b00000000000000000000000000000010; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //450000 CLK = 1'b0; #20000; //470000 WB_Inst = 32'b00100000000000100000000000000001; ID_Inst = 32'b00000000000000000010000000100000; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00100000000000111111111111111111; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b00010; MEM_CPUDataOut = 32'b00000000000000000000000000000011; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000100010100000100000; PCOut = 32'b00000000000000000000000000010000; CPUDataOut = 32'b00000000000000000000000000000011; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; #20000; //490000 CLK = 1'b0; #20000; //510000 WB_Inst = 32'b00100000000000111111111111111111; ID_Inst = 32'b00000000000000100010100000100000; EX_Inst = 32'b00000000000000000010000000100000; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00011; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000010000110011000000100000; PCOut = 32'b00000000000000000000000000010100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg2 = 32'b00000000000000000000000000000001; #20000; //530000 CLK = 1'b0; #20000; //550000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00000000010000110011000000100000; EX_Inst = 32'b00000000000000100010100000100000; MEM_Inst = 32'b00000000000000000010000000100000; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000000000011000; CLK = 1'b1; Reg3 = 32'b11111111111111111111111111111111; #20000; //570000 CLK = 1'b0; #20000; //590000 WB_Inst = 32'b00000000000000000010000000100000; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00000000010000110011000000100000; MEM_Inst = 32'b00000000000000100010100000100000; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000010000110011100000100001; PCOut = 32'b00000000000000000000000000011100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //610000 CLK = 1'b0; #20000; //630000 WB_Inst = 32'b00000000000000100010100000100000; ID_Inst = 32'b00000000010000110011100000100001; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00000000010000110011000000100000; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000011000000100000000100001; PCOut = 32'b00000000000000000000000000100000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000000; #20000; //650000 CLK = 1'b0; #20000; //670000 WB_Inst = 32'b00000000010000110011000000100000; ID_Inst = 32'b00000000011000000100000000100001; EX_Inst = 32'b00000000010000110011100000100001; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000100100000100001; PCOut = 32'b00000000000000000000000000100100; CPUDataOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000001; #20000; //690000 CLK = 1'b0; #20000; //710000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00000000000000000100100000100001; EX_Inst = 32'b00000000011000000100000000100001; MEM_Inst = 32'b00000000010000110011100000100001; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00000; MEM_CPUDataOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000000000101000; CPUDataOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000000; #20000; //730000 CLK = 1'b0; #20000; //750000 WB_Inst = 32'b00000000010000110011100000100001; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00000000000000000100100000100001; MEM_Inst = 32'b00000000011000000100000000100001; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00100000000010100000000000000000; PCOut = 32'b00000000000000000000000000101100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; #20000; //770000 CLK = 1'b0; #20000; //790000 WB_Inst = 32'b00000000011000000100000000100001; ID_Inst = 32'b00100000000010100000000000000000; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00000000000000000100100000100001; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b01000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00100000010010111111111111111111; PCOut = 32'b00000000000000000000000000110000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000000; #20000; //810000 CLK = 1'b0; #20000; //830000 WB_Inst = 32'b00000000000000000100100000100001; ID_Inst = 32'b00100000010010111111111111111111; EX_Inst = 32'b00100000000010100000000000000000; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b01001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00100000000011000000000000000001; PCOut = 32'b00000000000000000000000000110100; CLK = 1'b1; Reg8 = 32'b11111111111111111111111111111111; #20000; //850000 CLK = 1'b0; #20000; //870000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00100000000011000000000000000001; EX_Inst = 32'b00100000010010111111111111111111; MEM_Inst = 32'b00100000000010100000000000000000; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b00000; MEM_CPUDataOut = 32'b00000000000000000000000000001010; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000000000111000; CPUDataOut = 32'b00000000000000000000000000001010; CLK = 1'b1; Reg9 = 32'b00000000000000000000000000000000; #20000; //890000 CLK = 1'b0; #20000; //910000 WB_Inst = 32'b00100000000010100000000000000000; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00100000000011000000000000000001; MEM_Inst = 32'b00100000010010111111111111111111; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000000000000001011; Inst = 32'b00100100011011010000000000000000; PCOut = 32'b00000000000000000000000000111100; CPUDataOut = 32'b00000000000000000000000000001011; CLK = 1'b1; #20000; //930000 CLK = 1'b0; #20000; //950000 WB_Inst = 32'b00100000010010111111111111111111; ID_Inst = 32'b00100100011011010000000000000000; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00100000000011000000000000000001; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b01011; MEM_CPUDataOut = 32'b00000000000000000000000000001100; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00100100010011101111111111111111; PCOut = 32'b00000000000000000000000001000000; CPUDataOut = 32'b00000000000000000000000000001100; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg10 = 32'b00000000000000000000000000000000; #20000; //970000 CLK = 1'b0; #20000; //990000 WB_Inst = 32'b00100000000011000000000000000001; ID_Inst = 32'b00100100010011101111111111111111; EX_Inst = 32'b00100100011011010000000000000000; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b01101; WB_WriteReg = 5'b01100; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00100000000011110000000000000000; PCOut = 32'b00000000000000000000000001000100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg11 = 32'b00000000000000000000000000000000; #20000; //1010000 CLK = 1'b0; #20000; //1030000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00100000000011110000000000000000; EX_Inst = 32'b00100100010011101111111111111111; MEM_Inst = 32'b00100100011011010000000000000000; MEM_WriteReg = 5'b01101; EX_WriteReg = 5'b01110; WB_WriteReg = 5'b00000; MEM_CPUDataOut = 32'b00000000000000000000000000001101; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000000001001000; CPUDataOut = 32'b00000000000000000000000000001101; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg12 = 32'b00000000000000000000000000000001; #20000; //1050000 CLK = 1'b0; #20000; //1070000 WB_Inst = 32'b00100100011011010000000000000000; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00100000000011110000000000000000; MEM_Inst = 32'b00100100010011101111111111111111; MEM_WriteReg = 5'b01110; EX_WriteReg = 5'b01111; WB_WriteReg = 5'b01101; MEM_CPUDataOut = 32'b00000000000000000000000000001110; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000000000001000000000100100; PCOut = 32'b00000000000000000000000001001100; CPUDataOut = 32'b00000000000000000000000000001110; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //1090000 CLK = 1'b0; #20000; //1110000 WB_Inst = 32'b00100100010011101111111111111111; ID_Inst = 32'b00000000000000001000000000100100; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00100000000011110000000000000000; MEM_WriteReg = 5'b01111; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b01110; MEM_CPUDataOut = 32'b00000000000000000000000000001111; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000010000101000100000100100; PCOut = 32'b00000000000000000000000001010000; CPUDataOut = 32'b00000000000000000000000000001111; CLK = 1'b1; Reg13 = 32'b11111111111111111111111111111111; #20000; //1130000 CLK = 1'b0; #20000; //1150000 WB_Inst = 32'b00100000000011110000000000000000; ID_Inst = 32'b00000000010000101000100000100100; EX_Inst = 32'b00000000000000001000000000100100; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b10000; WB_WriteReg = 5'b01111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000011000101001000000100100; PCOut = 32'b00000000000000000000000001010100; CPUDataOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg14 = 32'b00000000000000000000000000000000; #20000; //1170000 CLK = 1'b0; #20000; //1190000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00000000011000101001000000100100; EX_Inst = 32'b00000000010000101000100000100100; MEM_Inst = 32'b00000000000000001000000000100100; MEM_WriteReg = 5'b10000; EX_WriteReg = 5'b10001; WB_WriteReg = 5'b00000; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000000001011000; CLK = 1'b1; Reg15 = 32'b00000000000000000000000000000000; #20000; //1210000 CLK = 1'b0; #20000; //1230000 WB_Inst = 32'b00000000000000001000000000100100; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00000000011000101001000000100100; MEM_Inst = 32'b00000000010000101000100000100100; MEM_WriteReg = 5'b10001; EX_WriteReg = 5'b10010; WB_WriteReg = 5'b10000; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00100000000100111111111111111111; PCOut = 32'b00000000000000000000000001011100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //1250000 CLK = 1'b0; #20000; //1270000 WB_Inst = 32'b00000000010000101000100000100100; ID_Inst = 32'b00100000000100111111111111111111; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00000000011000101001000000100100; MEM_WriteReg = 5'b10010; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b10001; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00110000000101000000000000000000; PCOut = 32'b00000000000000000000000001100000; CLK = 1'b1; Reg16 = 32'b00000000000000000000000000000000; #20000; //1290000 CLK = 1'b0; #20000; //1310000 WB_Inst = 32'b00000000011000101001000000100100; ID_Inst = 32'b00110000000101000000000000000000; EX_Inst = 32'b00100000000100111111111111111111; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b10011; WB_WriteReg = 5'b10010; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00110000010101010000000000000001; PCOut = 32'b00000000000000000000000001100100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg17 = 32'b00000000000000000000000000000001; #20000; //1330000 CLK = 1'b0; #20000; //1350000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00110000010101010000000000000001; EX_Inst = 32'b00110000000101000000000000000000; MEM_Inst = 32'b00100000000100111111111111111111; MEM_WriteReg = 5'b10011; EX_WriteReg = 5'b10100; WB_WriteReg = 5'b00000; MEM_CPUDataOut = 32'b00000000000000000000000000010011; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00110000010101101111111111111111; PCOut = 32'b00000000000000000000000001101000; CPUDataOut = 32'b00000000000000000000000000010011; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg18 = 32'b00000000000000000000000000000001; #20000; //1370000 CLK = 1'b0; #20000; //1390000 WB_Inst = 32'b00100000000100111111111111111111; ID_Inst = 32'b00110000010101101111111111111111; EX_Inst = 32'b00110000010101010000000000000001; MEM_Inst = 32'b00110000000101000000000000000000; MEM_WriteReg = 5'b10100; EX_WriteReg = 5'b10101; WB_WriteReg = 5'b10011; MEM_CPUDataOut = 32'b00000000000000000000000000010100; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00110000011101111111111111111111; PCOut = 32'b00000000000000000000000001101100; CPUDataOut = 32'b00000000000000000000000000010100; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //1410000 CLK = 1'b0; #20000; //1430000 WB_Inst = 32'b00110000000101000000000000000000; ID_Inst = 32'b00110000011101111111111111111111; EX_Inst = 32'b00110000010101101111111111111111; MEM_Inst = 32'b00110000010101010000000000000001; MEM_WriteReg = 5'b10101; EX_WriteReg = 5'b10110; WB_WriteReg = 5'b10100; MEM_CPUDataOut = 32'b00000000000000000000000000010101; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00111100000110000000000000000000; PCOut = 32'b00000000000000000000000001110000; CPUDataOut = 32'b00000000000000000000000000010101; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg19 = 32'b11111111111111111111111111111111; #20000; //1450000 CLK = 1'b0; #20000; //1470000 WB_Inst = 32'b00110000010101010000000000000001; ID_Inst = 32'b00111100000110000000000000000000; EX_Inst = 32'b00110000011101111111111111111111; MEM_Inst = 32'b00110000010101101111111111111111; MEM_WriteReg = 5'b10110; EX_WriteReg = 5'b10111; WB_WriteReg = 5'b10101; MEM_CPUDataOut = 32'b00000000000000000000000000010110; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00111100000110010000000000000001; PCOut = 32'b00000000000000000000000001110100; CPUDataOut = 32'b00000000000000000000000000010110; CLK = 1'b1; Reg20 = 32'b00000000000000000000000000000000; #20000; //1490000 CLK = 1'b0; #20000; //1510000 WB_Inst = 32'b00110000010101101111111111111111; ID_Inst = 32'b00111100000110010000000000000001; EX_Inst = 32'b00111100000110000000000000000000; MEM_Inst = 32'b00110000011101111111111111111111; MEM_WriteReg = 5'b10111; EX_WriteReg = 5'b11000; WB_WriteReg = 5'b10110; MEM_CPUDataOut = 32'b00000000000000000000000000010111; MEM_ALUOut = 32'b00000000000000001111111111111111; Inst = 32'b00111100000110100000000000000001; PCOut = 32'b00000000000000000000000001111000; CPUDataOut = 32'b00000000000000000000000000010111; ALUOut = 32'b00000000000000001111111111111111; CLK = 1'b1; Reg21 = 32'b00000000000000000000000000000001; #20000; //1530000 CLK = 1'b0; #20000; //1550000 WB_Inst = 32'b00110000011101111111111111111111; ID_Inst = 32'b00111100000110100000000000000001; EX_Inst = 32'b00111100000110010000000000000001; MEM_Inst = 32'b00111100000110000000000000000000; MEM_WriteReg = 5'b11000; EX_WriteReg = 5'b11001; WB_WriteReg = 5'b10111; MEM_CPUDataOut = 32'b00000000000000000000000000011000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000001111111111111111; Inst = 32'b00111100000110111111111111111111; PCOut = 32'b00000000000000000000000001111100; CPUDataOut = 32'b00000000000000000000000000011000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg22 = 32'b00000000000000000000000000000001; #20000; //1570000 CLK = 1'b0; #20000; //1590000 WB_Inst = 32'b00111100000110000000000000000000; ID_Inst = 32'b00111100000110111111111111111111; EX_Inst = 32'b00111100000110100000000000000001; MEM_Inst = 32'b00111100000110010000000000000001; MEM_WriteReg = 5'b11001; EX_WriteReg = 5'b11010; WB_WriteReg = 5'b11000; MEM_CPUDataOut = 32'b00000000000000000000000000011001; MEM_ALUOut = 32'b00000000000000010000000000000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000001110000000100101; PCOut = 32'b00000000000000000000000010000000; CPUDataOut = 32'b00000000000000000000000000011001; ALUOut = 32'b00000000000000010000000000000000; CLK = 1'b1; Reg23 = 32'b00000000000000001111111111111111; #20000; //1610000 CLK = 1'b0; #20000; //1630000 WB_Inst = 32'b00111100000110010000000000000001; ID_Inst = 32'b00000000000000001110000000100101; EX_Inst = 32'b00111100000110111111111111111111; MEM_Inst = 32'b00111100000110100000000000000001; MEM_WriteReg = 5'b11010; EX_WriteReg = 5'b11011; WB_WriteReg = 5'b11001; MEM_CPUDataOut = 32'b00000000000000000000000000011010; WB_ALUOut = 32'b00000000000000010000000000000000; Inst = 32'b00000000010000101110100000100101; PCOut = 32'b00000000000000000000000010000100; CPUDataOut = 32'b00000000000000000000000000011010; CLK = 1'b1; Reg24 = 32'b00000000000000000000000000000000; #20000; //1650000 CLK = 1'b0; #20000; //1670000 WB_Inst = 32'b00111100000110100000000000000001; ID_Inst = 32'b00000000010000101110100000100101; EX_Inst = 32'b00000000000000001110000000100101; MEM_Inst = 32'b00111100000110111111111111111111; MEM_WriteReg = 5'b11011; EX_WriteReg = 5'b11100; WB_WriteReg = 5'b11010; MEM_CPUDataOut = 32'b00000000000000000000000000011011; MEM_ALUOut = 32'b11111111111111110000000000000000; Inst = 32'b00000000010000111111000000100101; PCOut = 32'b00000000000000000000000010001000; CPUDataOut = 32'b00000000000000000000000000011011; ALUOut = 32'b11111111111111110000000000000000; CLK = 1'b1; Reg25 = 32'b00000000000000010000000000000000; #20000; //1690000 CLK = 1'b0; #20000; //1710000 WB_Inst = 32'b00111100000110111111111111111111; ID_Inst = 32'b00000000010000111111000000100101; EX_Inst = 32'b00000000010000101110100000100101; MEM_Inst = 32'b00000000000000001110000000100101; MEM_WriteReg = 5'b11100; EX_WriteReg = 5'b11101; WB_WriteReg = 5'b11011; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111110000000000000000; Inst = 32'b00110100000111110000000000000000; PCOut = 32'b00000000000000000000000010001100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg26 = 32'b00000000000000010000000000000000; #20000; //1730000 CLK = 1'b0; #20000; //1750000 WB_Inst = 32'b00000000000000001110000000100101; ID_Inst = 32'b00110100000111110000000000000000; EX_Inst = 32'b00000000010000111111000000100101; MEM_Inst = 32'b00000000010000101110100000100101; MEM_WriteReg = 5'b11101; EX_WriteReg = 5'b11110; WB_WriteReg = 5'b11100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00110100010001000000000000000001; PCOut = 32'b00000000000000000000000010010000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg27 = 32'b11111111111111110000000000000000; #20000; //1770000 CLK = 1'b0; #20000; //1790000 WB_Inst = 32'b00000000010000101110100000100101; ID_Inst = 32'b00110100010001000000000000000001; EX_Inst = 32'b00110100000111110000000000000000; MEM_Inst = 32'b00000000010000111111000000100101; MEM_WriteReg = 5'b11110; EX_WriteReg = 5'b11111; WB_WriteReg = 5'b11101; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00110111011001101111111111111110; PCOut = 32'b00000000000000000000000010010100; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg28 = 32'b00000000000000000000000000000000; #20000; //1810000 CLK = 1'b0; #20000; //1830000 WB_Inst = 32'b00000000010000111111000000100101; ID_Inst = 32'b00110111011001101111111111111110; EX_Inst = 32'b00110100010001000000000000000001; MEM_Inst = 32'b00110100000111110000000000000000; MEM_WriteReg = 5'b11111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b11110; MEM_CPUDataOut = 32'b00000000000000000000000000011111; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00110100011001111111111111111111; PCOut = 32'b00000000000000000000000010011000; CPUDataOut = 32'b00000000000000000000000000011111; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg29 = 32'b00000000000000000000000000000001; #20000; //1850000 CLK = 1'b0; #20000; //1870000 WB_Inst = 32'b00110100000111110000000000000000; ID_Inst = 32'b00110100011001111111111111111111; EX_Inst = 32'b00110111011001101111111111111110; MEM_Inst = 32'b00110100010001000000000000000001; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b11111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000100000000100111; PCOut = 32'b00000000000000000000000010011100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg30 = 32'b11111111111111111111111111111111; #20000; //1890000 CLK = 1'b0; #20000; //1910000 WB_Inst = 32'b00110100010001000000000000000001; ID_Inst = 32'b00000000000000000100000000100111; EX_Inst = 32'b00110100011001111111111111111111; MEM_Inst = 32'b00110111011001101111111111111110; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00100; MEM_ALUOut = 32'b11111111111111111111111111111110; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000010000100100100000100111; PCOut = 32'b00000000000000000000000010100000; ALUOut = 32'b11111111111111111111111111111110; CLK = 1'b1; Reg31 = 32'b00000000000000000000000000000000; #20000; //1930000 CLK = 1'b0; #20000; //1950000 WB_Inst = 32'b00110111011001101111111111111110; ID_Inst = 32'b00000000010000100100100000100111; EX_Inst = 32'b00000000000000000100000000100111; MEM_Inst = 32'b00110100011001111111111111111111; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00110; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00000000010000110101000000100111; PCOut = 32'b00000000000000000000000010100100; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000001; #20000; //1970000 CLK = 1'b0; #20000; //1990000 WB_Inst = 32'b00110100011001111111111111111111; ID_Inst = 32'b00000000010000110101000000100111; EX_Inst = 32'b00000000010000100100100000100111; MEM_Inst = 32'b00000000000000000100000000100111; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000000000100101100000000000; PCOut = 32'b00000000000000000000000010101000; CLK = 1'b1; Reg6 = 32'b11111111111111111111111111111110; #20000; //2010000 CLK = 1'b0; #20000; //2030000 WB_Inst = 32'b00000000000000000100000000100111; ID_Inst = 32'b00000000000000100101100000000000; EX_Inst = 32'b00000000010000110101000000100111; MEM_Inst = 32'b00000000010000100100100000100111; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b01000; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00000000000000100010000001000000; PCOut = 32'b00000000000000000000000010101100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b11111111111111111111111111111110; CLK = 1'b1; Reg7 = 32'b11111111111111111111111111111111; #20000; //2050000 CLK = 1'b0; #20000; //2070000 WB_Inst = 32'b00000000010000100100100000100111; ID_Inst = 32'b00000000000000100010000001000000; EX_Inst = 32'b00000000000000100101100000000000; MEM_Inst = 32'b00000000010000110101000000100111; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b01001; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00000000000000100010110000000000; PCOut = 32'b00000000000000000000000010110000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //2090000 CLK = 1'b0; #20000; //2110000 WB_Inst = 32'b00000000010000110101000000100111; ID_Inst = 32'b00000000000000100010110000000000; EX_Inst = 32'b00000000000000100010000001000000; MEM_Inst = 32'b00000000000000100101100000000000; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000100011011111000000; PCOut = 32'b00000000000000000000000010110100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg9 = 32'b11111111111111111111111111111110; #20000; //2130000 CLK = 1'b0; #20000; //2150000 WB_Inst = 32'b00000000000000100101100000000000; ID_Inst = 32'b00000000000000100011011111000000; EX_Inst = 32'b00000000000000100010110000000000; MEM_Inst = 32'b00000000000000100010000001000000; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b01011; MEM_ALUOut = 32'b00000000000000000000000000000010; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00100000000010110000000000010000; PCOut = 32'b00000000000000000000000010111000; ALUOut = 32'b00000000000000000000000000000010; CLK = 1'b1; #20000; //2170000 CLK = 1'b0; #20000; //2190000 WB_Inst = 32'b00000000000000100010000001000000; ID_Inst = 32'b00100000000010110000000000010000; EX_Inst = 32'b00000000000000100011011111000000; MEM_Inst = 32'b00000000000000100010110000000000; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_ALUOut = 32'b00000000000000010000000000000000; WB_ALUOut = 32'b00000000000000000000000000000010; Inst = 32'b00100000000011000000000000011111; PCOut = 32'b00000000000000000000000010111100; ALUOut = 32'b00000000000000010000000000000000; CLK = 1'b1; Reg11 = 32'b00000000000000000000000000000001; #20000; //2210000 CLK = 1'b0; #20000; //2230000 WB_Inst = 32'b00000000000000100010110000000000; ID_Inst = 32'b00100000000011000000000000011111; EX_Inst = 32'b00100000000010110000000000010000; MEM_Inst = 32'b00000000000000100011011111000000; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b00101; MEM_ALUOut = 32'b10000000000000000000000000000000; WB_ALUOut = 32'b00000000000000010000000000000000; Inst = 32'b00000000000000100011100000000100; PCOut = 32'b00000000000000000000000011000000; ALUOut = 32'b10000000000000000000000000000000; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000010; #20000; //2250000 CLK = 1'b0; #20000; //2270000 WB_Inst = 32'b00000000000000100011011111000000; ID_Inst = 32'b00000000000000100011100000000100; EX_Inst = 32'b00100000000011000000000000011111; MEM_Inst = 32'b00100000000010110000000000010000; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b00110; MEM_ALUOut = 32'b00000000000000000000000000010000; WB_ALUOut = 32'b10000000000000000000000000000000; Inst = 32'b00000000011000100100000000000100; PCOut = 32'b00000000000000000000000011000100; ALUOut = 32'b00000000000000000000000000010000; CLK = 1'b1; Reg5 = 32'b00000000000000010000000000000000; #20000; //2290000 CLK = 1'b0; #20000; //2310000 WB_Inst = 32'b00100000000010110000000000010000; ID_Inst = 32'b00000000011000100100000000000100; EX_Inst = 32'b00000000000000100011100000000100; MEM_Inst = 32'b00100000000011000000000000011111; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b01011; MEM_ALUOut = 32'b00000000000000000000000000011111; WB_ALUOut = 32'b00000000000000000000000000010000; Inst = 32'b00000000100000100100100000000100; PCOut = 32'b00000000000000000000000011001000; ALUOut = 32'b00000000000000000000000000011111; CLK = 1'b1; Reg6 = 32'b10000000000000000000000000000000; #20000; //2330000 CLK = 1'b0; #20000; //2350000 WB_Inst = 32'b00100000000011000000000000011111; ID_Inst = 32'b00000000100000100100100000000100; EX_Inst = 32'b00000000011000100100000000000100; MEM_Inst = 32'b00000000000000100011100000000100; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b01100; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000011111; Inst = 32'b00000001011000100101000000000100; PCOut = 32'b00000000000000000000000011001100; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg11 = 32'b00000000000000000000000000010000; #20000; //2370000 CLK = 1'b0; #20000; //2390000 WB_Inst = 32'b00000000000000100011100000000100; ID_Inst = 32'b00000001011000100101000000000100; EX_Inst = 32'b00000000100000100100100000000100; MEM_Inst = 32'b00000000011000100100000000000100; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; MEM_ALUOut = 32'b10000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000001100000100011000000000100; PCOut = 32'b00000000000000000000000011010000; ALUOut = 32'b10000000000000000000000000000000; CLK = 1'b1; Reg12 = 32'b00000000000000000000000000011111; #20000; //2410000 CLK = 1'b0; #20000; //2430000 WB_Inst = 32'b00000000011000100100000000000100; ID_Inst = 32'b00000001100000100011000000000100; EX_Inst = 32'b00000001011000100101000000000100; MEM_Inst = 32'b00000000100000100100100000000100; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b01000; MEM_ALUOut = 32'b00000000000000000000000000000100; WB_ALUOut = 32'b10000000000000000000000000000000; Inst = 32'b00000000000000000010000000101010; PCOut = 32'b00000000000000000000000011010100; ALUOut = 32'b00000000000000000000000000000100; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000001; #20000; //2450000 CLK = 1'b0; #20000; //2470000 WB_Inst = 32'b00000000100000100100100000000100; ID_Inst = 32'b00000000000000000010000000101010; EX_Inst = 32'b00000001100000100011000000000100; MEM_Inst = 32'b00000001011000100101000000000100; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b01001; MEM_ALUOut = 32'b00000000000000010000000000000000; WB_ALUOut = 32'b00000000000000000000000000000100; Inst = 32'b00000000010000000010100000101010; PCOut = 32'b00000000000000000000000011011000; ALUOut = 32'b00000000000000010000000000000000; CLK = 1'b1; Reg8 = 32'b10000000000000000000000000000000; #20000; //2490000 CLK = 1'b0; #20000; //2510000 WB_Inst = 32'b00000001011000100101000000000100; ID_Inst = 32'b00000000010000000010100000101010; EX_Inst = 32'b00000000000000000010000000101010; MEM_Inst = 32'b00000001100000100011000000000100; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01010; MEM_ALUOut = 32'b10000000000000000000000000000000; WB_ALUOut = 32'b00000000000000010000000000000000; Inst = 32'b00000000000000100011000000101010; PCOut = 32'b00000000000000000000000011011100; ALUOut = 32'b10000000000000000000000000000000; CLK = 1'b1; Reg9 = 32'b00000000000000000000000000000100; #20000; //2530000 CLK = 1'b0; #20000; //2550000 WB_Inst = 32'b00000001100000100011000000000100; ID_Inst = 32'b00000000000000100011000000101010; EX_Inst = 32'b00000000010000000010100000101010; MEM_Inst = 32'b00000000000000000010000000101010; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b10000000000000000000000000000000; Inst = 32'b00000000011000000011100000101010; PCOut = 32'b00000000000000000000000011100000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg10 = 32'b00000000000000010000000000000000; #20000; //2570000 CLK = 1'b0; #20000; //2590000 WB_Inst = 32'b00000000000000000010000000101010; ID_Inst = 32'b00000000011000000011100000101010; EX_Inst = 32'b00000000000000100011000000101010; MEM_Inst = 32'b00000000010000000010100000101010; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000110010000000101010; PCOut = 32'b00000000000000000000000011100100; CLK = 1'b1; #20000; //2610000 CLK = 1'b0; #20000; //2630000 WB_Inst = 32'b00000000010000000010100000101010; ID_Inst = 32'b00000000000000110010000000101010; EX_Inst = 32'b00000000011000000011100000101010; MEM_Inst = 32'b00000000000000100011000000101010; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000011000100010100000101010; PCOut = 32'b00000000000000000000000011101000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000000; #20000; //2650000 CLK = 1'b0; #20000; //2670000 WB_Inst = 32'b00000000000000100011000000101010; ID_Inst = 32'b00000000011000100010100000101010; EX_Inst = 32'b00000000000000110010000000101010; MEM_Inst = 32'b00000000011000000011100000101010; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101000000001100000000000000000; PCOut = 32'b00000000000000000000000011101100; CPUDataOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000000; #20000; //2690000 CLK = 1'b0; #20000; //2710000 WB_Inst = 32'b00000000011000000011100000101010; ID_Inst = 32'b00101000000001100000000000000000; EX_Inst = 32'b00000000011000100010100000101010; MEM_Inst = 32'b00000000000000110010000000101010; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00101000010001110000000000000000; PCOut = 32'b00000000000000000000000011110000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000001; #20000; //2730000 CLK = 1'b0; #20000; //2750000 WB_Inst = 32'b00000000000000110010000000101010; ID_Inst = 32'b00101000010001110000000000000000; EX_Inst = 32'b00101000000001100000000000000000; MEM_Inst = 32'b00000000011000100010100000101010; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00101000000001000000000000000001; PCOut = 32'b00000000000000000000000011110100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //2770000 CLK = 1'b0; #20000; //2790000 WB_Inst = 32'b00000000011000100010100000101010; ID_Inst = 32'b00101000000001000000000000000001; EX_Inst = 32'b00101000010001110000000000000000; MEM_Inst = 32'b00101000000001100000000000000000; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101000011001010000000000000000; PCOut = 32'b00000000000000000000000011111000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //2810000 CLK = 1'b0; #20000; //2830000 WB_Inst = 32'b00101000000001100000000000000000; ID_Inst = 32'b00101000011001010000000000000000; EX_Inst = 32'b00101000000001000000000000000001; MEM_Inst = 32'b00101000010001110000000000000000; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00101000000001101111111111111111; PCOut = 32'b00000000000000000000000011111100; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000001; #20000; //2850000 CLK = 1'b0; #20000; //2870000 WB_Inst = 32'b00101000010001110000000000000000; ID_Inst = 32'b00101000000001101111111111111111; EX_Inst = 32'b00101000011001010000000000000000; MEM_Inst = 32'b00101000000001000000000000000001; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101000011001110000000000000001; PCOut = 32'b00000000000000000000000100000000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000000; #20000; //2890000 CLK = 1'b0; #20000; //2910000 WB_Inst = 32'b00101000000001000000000000000001; ID_Inst = 32'b00101000011001110000000000000001; EX_Inst = 32'b00101000000001101111111111111111; MEM_Inst = 32'b00101000011001010000000000000000; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101000010001001111111111111111; PCOut = 32'b00000000000000000000000100000100; CPUDataOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000000; #20000; //2930000 CLK = 1'b0; #20000; //2950000 WB_Inst = 32'b00101000011001010000000000000000; ID_Inst = 32'b00101000010001001111111111111111; EX_Inst = 32'b00101000011001110000000000000001; MEM_Inst = 32'b00101000000001101111111111111111; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00101100000001010000000000000000; PCOut = 32'b00000000000000000000000100001000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000001; #20000; //2970000 CLK = 1'b0; #20000; //2990000 WB_Inst = 32'b00101000000001101111111111111111; ID_Inst = 32'b00101100000001010000000000000000; EX_Inst = 32'b00101000010001001111111111111111; MEM_Inst = 32'b00101000011001110000000000000001; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00101100010001100000000000000000; PCOut = 32'b00000000000000000000000100001100; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //3010000 CLK = 1'b0; #20000; //3030000 WB_Inst = 32'b00101000011001110000000000000001; ID_Inst = 32'b00101100010001100000000000000000; EX_Inst = 32'b00101100000001010000000000000000; MEM_Inst = 32'b00101000010001001111111111111111; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101100000001110000000000000001; PCOut = 32'b00000000000000000000000100010000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //3050000 CLK = 1'b0; #20000; //3070000 WB_Inst = 32'b00101000010001001111111111111111; ID_Inst = 32'b00101100000001110000000000000001; EX_Inst = 32'b00101100010001100000000000000000; MEM_Inst = 32'b00101100000001010000000000000000; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00101100011001000000000000000000; PCOut = 32'b00000000000000000000000100010100; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000001; #20000; //3090000 CLK = 1'b0; #20000; //3110000 WB_Inst = 32'b00101100000001010000000000000000; ID_Inst = 32'b00101100011001000000000000000000; EX_Inst = 32'b00101100000001110000000000000001; MEM_Inst = 32'b00101100010001100000000000000000; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b00000000000000000000000000000000; Inst = 32'b00101100000001011111111111111111; PCOut = 32'b00000000000000000000000100011000; CPUDataOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000000; #20000; //3130000 CLK = 1'b0; #20000; //3150000 WB_Inst = 32'b00101100010001100000000000000000; ID_Inst = 32'b00101100000001011111111111111111; EX_Inst = 32'b00101100011001000000000000000000; MEM_Inst = 32'b00101100000001110000000000000001; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101100011001100000000000000001; PCOut = 32'b00000000000000000000000100011100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000000; #20000; //3170000 CLK = 1'b0; #20000; //3190000 WB_Inst = 32'b00101100000001110000000000000001; ID_Inst = 32'b00101100011001100000000000000001; EX_Inst = 32'b00101100000001011111111111111111; MEM_Inst = 32'b00101100011001000000000000000000; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00101100010001111111111111111111; PCOut = 32'b00000000000000000000000100100000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //3210000 CLK = 1'b0; #20000; //3230000 WB_Inst = 32'b00101100011001000000000000000000; ID_Inst = 32'b00101100010001111111111111111111; EX_Inst = 32'b00101100011001100000000000000001; MEM_Inst = 32'b00101100000001011111111111111111; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000010000000101011; PCOut = 32'b00000000000000000000000100100100; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //3250000 CLK = 1'b0; #20000; //3270000 WB_Inst = 32'b00101100000001011111111111111111; ID_Inst = 32'b00000000000000000010000000101011; EX_Inst = 32'b00101100010001111111111111111111; MEM_Inst = 32'b00101100011001100000000000000001; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000010000000010100000101011; PCOut = 32'b00000000000000000000000100101000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //3290000 CLK = 1'b0; #20000; //3310000 WB_Inst = 32'b00101100011001100000000000000001; ID_Inst = 32'b00000000010000000010100000101011; EX_Inst = 32'b00000000000000000010000000101011; MEM_Inst = 32'b00101100010001111111111111111111; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000100011000000101011; PCOut = 32'b00000000000000000000000100101100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000001; #20000; //3330000 CLK = 1'b0; #20000; //3350000 WB_Inst = 32'b00101100010001111111111111111111; ID_Inst = 32'b00000000000000100011000000101011; EX_Inst = 32'b00000000010000000010100000101011; MEM_Inst = 32'b00000000000000000010000000101011; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000011000000011100000101011; PCOut = 32'b00000000000000000000000100110000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //3370000 CLK = 1'b0; #20000; //3390000 WB_Inst = 32'b00000000000000000010000000101011; ID_Inst = 32'b00000000011000000011100000101011; EX_Inst = 32'b00000000000000100011000000101011; MEM_Inst = 32'b00000000010000000010100000101011; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000110010000000101011; PCOut = 32'b00000000000000000000000100110100; CLK = 1'b1; #20000; //3410000 CLK = 1'b0; #20000; //3430000 WB_Inst = 32'b00000000010000000010100000101011; ID_Inst = 32'b00000000000000110010000000101011; EX_Inst = 32'b00000000011000000011100000101011; MEM_Inst = 32'b00000000000000100011000000101011; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000011000100010100000101011; PCOut = 32'b00000000000000000000000100111000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //3450000 CLK = 1'b0; #20000; //3470000 WB_Inst = 32'b00000000000000100011000000101011; ID_Inst = 32'b00000000011000100010100000101011; EX_Inst = 32'b00000000000000110010000000101011; MEM_Inst = 32'b00000000011000000011100000101011; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00100001001001110001000000000000; PCOut = 32'b00000000000000000000000100111100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000000; #20000; //3490000 CLK = 1'b0; #20000; //3510000 WB_Inst = 32'b00000000011000000011100000101011; ID_Inst = 32'b00100001001001110001000000000000; EX_Inst = 32'b00000000011000100010100000101011; MEM_Inst = 32'b00000000000000110010000000101011; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00111100000010001000000000000000; PCOut = 32'b00000000000000000000000101000000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000001; #20000; //3530000 CLK = 1'b0; #20000; //3550000 WB_Inst = 32'b00000000000000110010000000101011; ID_Inst = 32'b00111100000010001000000000000000; EX_Inst = 32'b00100001001001110001000000000000; MEM_Inst = 32'b00000000011000100010100000101011; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000010000110011000000101011; PCOut = 32'b00000000000000000000000101000100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000000; #20000; //3570000 CLK = 1'b0; #20000; //3590000 WB_Inst = 32'b00000000011000100010100000101011; ID_Inst = 32'b00000000010000110011000000101011; EX_Inst = 32'b00111100000010001000000000000000; MEM_Inst = 32'b00100001001001110001000000000000; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000001000000000100; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00100000000001000000000000000100; PCOut = 32'b00000000000000000000000101001000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000001000000000100; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000001; #20000; //3610000 CLK = 1'b0; #20000; //3630000 WB_Inst = 32'b00100001001001110001000000000000; ID_Inst = 32'b00100000000001000000000000000100; EX_Inst = 32'b00000000010000110011000000101011; MEM_Inst = 32'b00111100000010001000000000000000; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b10000000000000000000000000000000; MEM_ALUOut = 32'b10000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000001000000000100; Inst = 32'b00000000000000100100100000000011; PCOut = 32'b00000000000000000000000101001100; CPUDataOut = 32'b10000000000000000000000000000000; ALUOut = 32'b10000000000000000000000000000000; CLK = 1'b1; #20000; //3650000 CLK = 1'b0; #20000; //3670000 WB_Inst = 32'b00111100000010001000000000000000; ID_Inst = 32'b00000000000000100100100000000011; EX_Inst = 32'b00100000000001000000000000000100; MEM_Inst = 32'b00000000010000110011000000101011; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01000; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b10000000000000000000000000000000; Inst = 32'b00000000000000100101000001000011; PCOut = 32'b00000000000000000000000101010000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg7 = 32'b00000000000000000001000000000100; #20000; //3690000 CLK = 1'b0; #20000; //3710000 WB_Inst = 32'b00000000010000110011000000101011; ID_Inst = 32'b00000000000000100101000001000011; EX_Inst = 32'b00000000000000100100100000000011; MEM_Inst = 32'b00100000000001000000000000000100; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000100; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000001110101100100000011; PCOut = 32'b00000000000000000000000101010100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000100; CLK = 1'b1; #20000; //3730000 CLK = 1'b0; #20000; //3750000 WB_Inst = 32'b00100000000001000000000000000100; ID_Inst = 32'b00000000000001110101100100000011; EX_Inst = 32'b00000000000000100101000001000011; MEM_Inst = 32'b00000000000000100100100000000011; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b00100; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00000000000000000000000000000100; Inst = 32'b00000000000010000110000100000011; PCOut = 32'b00000000000000000000000101011000; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //3770000 CLK = 1'b0; #20000; //3790000 WB_Inst = 32'b00000000000000100100100000000011; ID_Inst = 32'b00000000000010000110000100000011; EX_Inst = 32'b00000000000001110101100100000011; MEM_Inst = 32'b00000000000000100101000001000011; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b01001; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000100100100000000111; PCOut = 32'b00000000000000000000000101011100; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000100; #20000; //3810000 CLK = 1'b0; #20000; //3830000 WB_Inst = 32'b00000000000000100101000001000011; ID_Inst = 32'b00000000000000100100100000000111; EX_Inst = 32'b00000000000010000110000100000011; MEM_Inst = 32'b00000000000001110101100100000011; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000001000000000100; MEM_ALUOut = 32'b00000000000000000000000100000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000010000100101000000000111; PCOut = 32'b00000000000000000000000101100000; CPUDataOut = 32'b00000000000000000001000000000100; ALUOut = 32'b00000000000000000000000100000000; CLK = 1'b1; Reg9 = 32'b00000000000000000000000000000001; #20000; //3850000 CLK = 1'b0; #20000; //3870000 WB_Inst = 32'b00000000000001110101100100000011; ID_Inst = 32'b00000000010000100101000000000111; EX_Inst = 32'b00000000000000100100100000000111; MEM_Inst = 32'b00000000000010000110000100000011; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b01011; MEM_CPUDataOut = 32'b10000000000000000000000000000000; MEM_ALUOut = 32'b11111000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000100000000; Inst = 32'b00000000100001110101100000000111; PCOut = 32'b00000000000000000000000101100100; CPUDataOut = 32'b10000000000000000000000000000000; ALUOut = 32'b11111000000000000000000000000000; CLK = 1'b1; Reg10 = 32'b00000000000000000000000000000000; #20000; //3890000 CLK = 1'b0; #20000; //3910000 WB_Inst = 32'b00000000000010000110000100000011; ID_Inst = 32'b00000000100001110101100000000111; EX_Inst = 32'b00000000010000100101000000000111; MEM_Inst = 32'b00000000000000100100100000000111; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b01100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b11111000000000000000000000000000; Inst = 32'b00000000100010000110000000000111; PCOut = 32'b00000000000000000000000101101000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg11 = 32'b00000000000000000000000100000000; #20000; //3930000 CLK = 1'b0; #20000; //3950000 WB_Inst = 32'b00000000000000100100100000000111; ID_Inst = 32'b00000000100010000110000000000111; EX_Inst = 32'b00000000100001110101100000000111; MEM_Inst = 32'b00000000010000100101000000000111; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b01001; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000100010100000000010; PCOut = 32'b00000000000000000000000101101100; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg12 = 32'b11111000000000000000000000000000; #20000; //3970000 CLK = 1'b0; #20000; //3990000 WB_Inst = 32'b00000000010000100101000000000111; ID_Inst = 32'b00000000000000100010100000000010; EX_Inst = 32'b00000000100010000110000000000111; MEM_Inst = 32'b00000000100001110101100000000111; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000001000000000100; MEM_ALUOut = 32'b00000000000000000000000100000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000100011000001000010; PCOut = 32'b00000000000000000000000101110000; CPUDataOut = 32'b00000000000000000001000000000100; ALUOut = 32'b00000000000000000000000100000000; CLK = 1'b1; #20000; //4010000 CLK = 1'b0; #20000; //4030000 WB_Inst = 32'b00000000100001110101100000000111; ID_Inst = 32'b00000000000000100011000001000010; EX_Inst = 32'b00000000000000100010100000000010; MEM_Inst = 32'b00000000100010000110000000000111; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b01011; MEM_CPUDataOut = 32'b10000000000000000000000000000000; MEM_ALUOut = 32'b11111000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000100000000; Inst = 32'b00000000000001110100100100000010; PCOut = 32'b00000000000000000000000101110100; CPUDataOut = 32'b10000000000000000000000000000000; ALUOut = 32'b11111000000000000000000000000000; CLK = 1'b1; #20000; //4050000 CLK = 1'b0; #20000; //4070000 WB_Inst = 32'b00000000100010000110000000000111; ID_Inst = 32'b00000000000001110100100100000010; EX_Inst = 32'b00000000000000100011000001000010; MEM_Inst = 32'b00000000000000100010100000000010; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b01100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b11111000000000000000000000000000; Inst = 32'b00000000000010000101000100000010; PCOut = 32'b00000000000000000000000101111000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //4090000 CLK = 1'b0; #20000; //4110000 WB_Inst = 32'b00000000000000100010100000000010; ID_Inst = 32'b00000000000010000101000100000010; EX_Inst = 32'b00000000000001110100100100000010; MEM_Inst = 32'b00000000000000100011000001000010; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00101; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000100101100000000010; PCOut = 32'b00000000000000000000000101111100; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //4130000 CLK = 1'b0; #20000; //4150000 WB_Inst = 32'b00000000000000100011000001000010; ID_Inst = 32'b00000000000000100101100000000010; EX_Inst = 32'b00000000000010000101000100000010; MEM_Inst = 32'b00000000000001110100100100000010; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000001000000000100; MEM_ALUOut = 32'b00000000000000000000000100000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000010000100110000000000110; PCOut = 32'b00000000000000000000000110000000; CPUDataOut = 32'b00000000000000000001000000000100; ALUOut = 32'b00000000000000000000000100000000; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000001; #20000; //4170000 CLK = 1'b0; #20000; //4190000 WB_Inst = 32'b00000000000001110100100100000010; ID_Inst = 32'b00000000010000100110000000000110; EX_Inst = 32'b00000000000000100101100000000010; MEM_Inst = 32'b00000000000010000101000100000010; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b01001; MEM_CPUDataOut = 32'b10000000000000000000000000000000; MEM_ALUOut = 32'b00001000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000100000000; Inst = 32'b00000000100001110100100000000110; PCOut = 32'b00000000000000000000000110000100; CPUDataOut = 32'b10000000000000000000000000000000; ALUOut = 32'b00001000000000000000000000000000; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000000; #20000; //4210000 CLK = 1'b0; #20000; //4230000 WB_Inst = 32'b00000000000010000101000100000010; ID_Inst = 32'b00000000100001110100100000000110; EX_Inst = 32'b00000000010000100110000000000110; MEM_Inst = 32'b00000000000000100101100000000010; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b00001000000000000000000000000000; Inst = 32'b00000000100010000101000000000110; PCOut = 32'b00000000000000000000000110001000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg9 = 32'b00000000000000000000000100000000; #20000; //4250000 CLK = 1'b0; #20000; //4270000 WB_Inst = 32'b00000000000000100101100000000010; ID_Inst = 32'b00000000100010000101000000000110; EX_Inst = 32'b00000000100001110100100000000110; MEM_Inst = 32'b00000000010000100110000000000110; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b01011; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000000010000000100010; PCOut = 32'b00000000000000000000000110001100; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg10 = 32'b00001000000000000000000000000000; #20000; //4290000 CLK = 1'b0; #20000; //4310000 WB_Inst = 32'b00000000010000100110000000000110; ID_Inst = 32'b00000000000000000010000000100010; EX_Inst = 32'b00000000100010000101000000000110; MEM_Inst = 32'b00000000100001110100100000000110; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b01100; MEM_CPUDataOut = 32'b00000000000000000001000000000100; MEM_ALUOut = 32'b00000000000000000000000100000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000100010100000100010; PCOut = 32'b00000000000000000000000110010000; CPUDataOut = 32'b00000000000000000001000000000100; ALUOut = 32'b00000000000000000000000100000000; CLK = 1'b1; Reg11 = 32'b00000000000000000000000000000001; #20000; //4330000 CLK = 1'b0; #20000; //4350000 WB_Inst = 32'b00000000100001110100100000000110; ID_Inst = 32'b00000000000000100010100000100010; EX_Inst = 32'b00000000000000000010000000100010; MEM_Inst = 32'b00000000100010000101000000000110; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01001; MEM_CPUDataOut = 32'b10000000000000000000000000000000; MEM_ALUOut = 32'b00001000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000100000000; Inst = 32'b00000000010000000011000000100010; PCOut = 32'b00000000000000000000000110010100; CPUDataOut = 32'b10000000000000000000000000000000; ALUOut = 32'b00001000000000000000000000000000; CLK = 1'b1; Reg12 = 32'b00000000000000000000000000000000; #20000; //4370000 CLK = 1'b0; #20000; //4390000 WB_Inst = 32'b00000000100010000101000000000110; ID_Inst = 32'b00000000010000000011000000100010; EX_Inst = 32'b00000000000000100010100000100010; MEM_Inst = 32'b00000000000000000010000000100010; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00001000000000000000000000000000; Inst = 32'b00000000010000110011100000100010; PCOut = 32'b00000000000000000000000110011000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; #20000; //4410000 CLK = 1'b0; #20000; //4430000 WB_Inst = 32'b00000000000000000010000000100010; ID_Inst = 32'b00000000010000110011100000100010; EX_Inst = 32'b00000000010000000011000000100010; MEM_Inst = 32'b00000000000000100010100000100010; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000011000100100000000100010; PCOut = 32'b00000000000000000000000110011100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; #20000; //4450000 CLK = 1'b0; #20000; //4470000 WB_Inst = 32'b00000000000000100010100000100010; ID_Inst = 32'b00000000011000100100000000100010; EX_Inst = 32'b00000000010000110011100000100010; MEM_Inst = 32'b00000000010000000011000000100010; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000000000000100100000100011; PCOut = 32'b00000000000000000000000110100000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg4 = 32'b00000000000000000000000000000000; #20000; //4490000 CLK = 1'b0; #20000; //4510000 WB_Inst = 32'b00000000010000000011000000100010; ID_Inst = 32'b00000000000000000100100000100011; EX_Inst = 32'b00000000011000100100000000100010; MEM_Inst = 32'b00000000010000110011100000100010; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000010; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000100101000000100011; PCOut = 32'b00000000000000000000000110100100; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000010; CLK = 1'b1; Reg5 = 32'b11111111111111111111111111111111; #20000; //4530000 CLK = 1'b0; #20000; //4550000 WB_Inst = 32'b00000000010000110011100000100010; ID_Inst = 32'b00000000000000100101000000100011; EX_Inst = 32'b00000000000000000100100000100011; MEM_Inst = 32'b00000000011000100100000000100010; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b11111111111111111111111111111110; WB_ALUOut = 32'b00000000000000000000000000000010; Inst = 32'b00000000010000000101100000100011; PCOut = 32'b00000000000000000000000110101000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b11111111111111111111111111111110; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000001; #20000; //4570000 CLK = 1'b0; #20000; //4590000 WB_Inst = 32'b00000000011000100100000000100010; ID_Inst = 32'b00000000010000000101100000100011; EX_Inst = 32'b00000000000000100101000000100011; MEM_Inst = 32'b00000000000000000100100000100011; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b01010; WB_WriteReg = 5'b01000; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00000000010000110110000000100011; PCOut = 32'b00000000000000000000000110101100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000010; #20000; //4610000 CLK = 1'b0; #20000; //4630000 WB_Inst = 32'b00000000000000000100100000100011; ID_Inst = 32'b00000000010000110110000000100011; EX_Inst = 32'b00000000010000000101100000100011; MEM_Inst = 32'b00000000000000100101000000100011; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_WriteReg = 5'b01001; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000011000100110100000100011; PCOut = 32'b00000000000000000000000110110000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg8 = 32'b11111111111111111111111111111110; #20000; //4650000 CLK = 1'b0; #20000; //4670000 WB_Inst = 32'b00000000000000100101000000100011; ID_Inst = 32'b00000000011000100110100000100011; EX_Inst = 32'b00000000010000110110000000100011; MEM_Inst = 32'b00000000010000000101100000100011; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b01010; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000001; WB_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000000000000010000000100110; PCOut = 32'b00000000000000000000000110110100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; Reg9 = 32'b00000000000000000000000000000000; #20000; //4690000 CLK = 1'b0; #20000; //4710000 WB_Inst = 32'b00000000010000000101100000100011; ID_Inst = 32'b00000000000000000010000000100110; EX_Inst = 32'b00000000011000100110100000100011; MEM_Inst = 32'b00000000010000110110000000100011; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b01101; WB_WriteReg = 5'b01011; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00000000000000000000000000000010; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000011000110010100000100110; PCOut = 32'b00000000000000000000000110111000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00000000000000000000000000000010; CLK = 1'b1; Reg10 = 32'b11111111111111111111111111111111; #20000; //4730000 CLK = 1'b0; #20000; //4750000 WB_Inst = 32'b00000000010000110110000000100011; ID_Inst = 32'b00000000011000110010100000100110; EX_Inst = 32'b00000000000000000010000000100110; MEM_Inst = 32'b00000000011000100110100000100011; MEM_WriteReg = 5'b01101; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01100; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b11111111111111111111111111111110; WB_ALUOut = 32'b00000000000000000000000000000010; Inst = 32'b00000000010000110011000000100110; PCOut = 32'b00000000000000000000000110111100; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b11111111111111111111111111111110; CLK = 1'b1; #20000; //4770000 CLK = 1'b0; #20000; //4790000 WB_Inst = 32'b00000000011000100110100000100011; ID_Inst = 32'b00000000010000110011000000100110; EX_Inst = 32'b00000000011000110010100000100110; MEM_Inst = 32'b00000000000000000010000000100110; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b01101; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00111000000001110000000000000000; PCOut = 32'b00000000000000000000000111000000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg12 = 32'b00000000000000000000000000000010; #20000; //4810000 CLK = 1'b0; #20000; //4830000 WB_Inst = 32'b00000000000000000010000000100110; ID_Inst = 32'b00111000000001110000000000000000; EX_Inst = 32'b00000000010000110011000000100110; MEM_Inst = 32'b00000000011000110010100000100110; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b11111111111111111111111111111111; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00111000011010001111111111111111; PCOut = 32'b00000000000000000000000111000100; CPUDataOut = 32'b11111111111111111111111111111111; CLK = 1'b1; Reg13 = 32'b11111111111111111111111111111110; #20000; //4850000 CLK = 1'b0; #20000; //4870000 WB_Inst = 32'b00000000011000110010100000100110; ID_Inst = 32'b00111000011010001111111111111111; EX_Inst = 32'b00111000000001110000000000000000; MEM_Inst = 32'b00000000010000110011000000100110; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00111000010010011111111111111111; PCOut = 32'b00000000000000000000000111001000; ALUOut = 32'b11111111111111111111111111111110; CLK = 1'b1; #20000; //4890000 CLK = 1'b0; #20000; //4910000 WB_Inst = 32'b00000000010000110011000000100110; ID_Inst = 32'b00111000010010011111111111111111; EX_Inst = 32'b00111000011010001111111111111111; MEM_Inst = 32'b00111000000001110000000000000000; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000000010; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b11111111111111111111111111111110; Inst = 32'b00000000000000000000000000010001; PCOut = 32'b00000000000000000000000111001100; CPUDataOut = 32'b00000000000000000000000000000010; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg5 = 32'b00000000000000000000000000000000; #20000; //4930000 CLK = 1'b0; #20000; //4950000 WB_Inst = 32'b00111000000001110000000000000000; ID_Inst = 32'b00000000000000000000000000010001; EX_Inst = 32'b00111000010010011111111111111111; MEM_Inst = 32'b00111000011010001111111111111111; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b11111111111111111111111111111110; MEM_ALUOut = 32'b11111111111111110000000000000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000000000000010011; PCOut = 32'b00000000000000000000000111010000; CPUDataOut = 32'b11111111111111111111111111111110; ALUOut = 32'b11111111111111110000000000000000; CLK = 1'b1; Reg6 = 32'b11111111111111111111111111111110; #20000; //4970000 CLK = 1'b0; #20000; //4990000 WB_Inst = 32'b00111000011010001111111111111111; ID_Inst = 32'b00000000000000000000000000010011; EX_Inst = 32'b00000000000000000000000000010001; MEM_Inst = 32'b00111000010010011111111111111111; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b01000; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000001111111111111110; WB_ALUOut = 32'b11111111111111110000000000000000; Inst = 32'b00000000000000000010000000010000; PCOut = 32'b00000000000000000000000111010100; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000001111111111111110; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000000; #20000; //5010000 CLK = 1'b0; #20000; //5030000 WB_Inst = 32'b00111000010010011111111111111111; ID_Inst = 32'b00000000000000000010000000010000; EX_Inst = 32'b00000000000000000000000000010011; MEM_Inst = 32'b00000000000000000000000000010001; MEM_RegWrite = 1'b0; MEM_WriteReg = 5'b00000; WB_WriteReg = 5'b01001; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000001111111111111110; Inst = 32'b00000000000000000010100000010010; PCOut = 32'b00000000000000000000000111011000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg8 = 32'b11111111111111110000000000000000; #20000; //5050000 CLK = 1'b0; #20000; //5070000 WB_Inst = 32'b00000000000000000000000000010001; ID_Inst = 32'b00000000000000000010100000010010; EX_Inst = 32'b00000000000000000010000000010000; MEM_Inst = 32'b00000000000000000000000000010011; EX_RegWrite = 1'b1; EX_WriteReg = 5'b00100; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000010000000000000000010001; PCOut = 32'b00000000000000000000000111011100; CLK = 1'b1; Reg9 = 32'b00000000000000001111111111111110; #20000; //5090000 CLK = 1'b0; #20000; //5110000 WB_Inst = 32'b00000000000000000000000000010011; ID_Inst = 32'b00000000010000000000000000010001; EX_Inst = 32'b00000000000000000010100000010010; MEM_Inst = 32'b00000000000000000010000000010000; MEM_RegWrite = 1'b1; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; Inst = 32'b00000000010000000000000000010011; PCOut = 32'b00000000000000000000000111100000; CLK = 1'b1; #20000; //5130000 CLK = 1'b0; #20000; //5150000 WB_Inst = 32'b00000000000000000010000000010000; ID_Inst = 32'b00000000010000000000000000010011; EX_Inst = 32'b00000000010000000000000000010001; MEM_Inst = 32'b00000000000000000010100000010010; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00000; WB_RegWrite = 1'b1; WB_WriteReg = 5'b00100; Inst = 32'b00000000000000000011000000010000; PCOut = 32'b00000000000000000000000111100100; CLK = 1'b1; #20000; //5170000 CLK = 1'b0; #20000; //5190000 WB_Inst = 32'b00000000000000000010100000010010; ID_Inst = 32'b00000000000000000011000000010000; EX_Inst = 32'b00000000010000000000000000010011; MEM_Inst = 32'b00000000010000000000000000010001; MEM_RegWrite = 1'b0; MEM_WriteReg = 5'b00000; WB_WriteReg = 5'b00101; Inst = 32'b00000000000000000011100000010010; PCOut = 32'b00000000000000000000000111101000; CLK = 1'b1; #20000; //5210000 CLK = 1'b0; #20000; //5230000 WB_Inst = 32'b00000000010000000000000000010001; ID_Inst = 32'b00000000000000000011100000010010; EX_Inst = 32'b00000000000000000011000000010000; MEM_Inst = 32'b00000000010000000000000000010011; EX_RegWrite = 1'b1; EX_WriteReg = 5'b00110; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00000; Inst = 32'b00000000011000000000000000010001; PCOut = 32'b00000000000000000000000111101100; CLK = 1'b1; #20000; //5250000 CLK = 1'b0; #20000; //5270000 WB_Inst = 32'b00000000010000000000000000010011; ID_Inst = 32'b00000000011000000000000000010001; EX_Inst = 32'b00000000000000000011100000010010; MEM_Inst = 32'b00000000000000000011000000010000; MEM_RegWrite = 1'b1; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; MEM_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000011000000000000000010011; PCOut = 32'b00000000000000000000000111110000; ALUOut = 32'b00000000000000000000000000000001; CLK = 1'b1; #20000; //5290000 CLK = 1'b0; #20000; //5310000 WB_Inst = 32'b00000000000000000011000000010000; ID_Inst = 32'b00000000011000000000000000010011; EX_Inst = 32'b00000000011000000000000000010001; MEM_Inst = 32'b00000000000000000011100000010010; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00000; WB_RegWrite = 1'b1; WB_WriteReg = 5'b00110; WB_ALUOut = 32'b00000000000000000000000000000001; Inst = 32'b00000000000000000100000000010000; PCOut = 32'b00000000000000000000000111110100; CLK = 1'b1; #20000; //5330000 CLK = 1'b0; #20000; //5350000 WB_Inst = 32'b00000000000000000011100000010010; ID_Inst = 32'b00000000000000000100000000010000; EX_Inst = 32'b00000000011000000000000000010011; MEM_Inst = 32'b00000000011000000000000000010001; MEM_RegWrite = 1'b0; MEM_WriteReg = 5'b00000; WB_WriteReg = 5'b00111; MEM_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000100100000010010; PCOut = 32'b00000000000000000000000111111000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg6 = 32'b00000000000000000000000000000001; #20000; //5370000 CLK = 1'b0; #20000; //5390000 WB_Inst = 32'b00000000011000000000000000010001; ID_Inst = 32'b00000000000000000100100000010010; EX_Inst = 32'b00000000000000000100000000010000; MEM_Inst = 32'b00000000011000000000000000010011; EX_RegWrite = 1'b1; EX_WriteReg = 5'b01000; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00111100000000100001000000000000; PCOut = 32'b00000000000000000000000111111100; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000000001; #20000; //5410000 CLK = 1'b0; #20000; //5430000 WB_Inst = 32'b00000000011000000000000000010011; ID_Inst = 32'b00111100000000100001000000000000; EX_Inst = 32'b00000000000000000100100000010010; MEM_Inst = 32'b00000000000000000100000000010000; MEM_RegWrite = 1'b1; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; MEM_ALUOut = 32'b11111111111111111111111111111111; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000001000000000; ALUOut = 32'b11111111111111111111111111111111; CLK = 1'b1; #20000; //5450000 CLK = 1'b0; #20000; //5470000 WB_Inst = 32'b00000000000000000100000000010000; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b00111100000000100001000000000000; MEM_Inst = 32'b00000000000000000100100000010010; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00010; WB_RegWrite = 1'b1; WB_WriteReg = 5'b01000; WB_ALUOut = 32'b11111111111111111111111111111111; PCOut = 32'b00000000000000000000001000000100; CLK = 1'b1; #20000; //5490000 CLK = 1'b0; #20000; //5510000 WB_Inst = 32'b00000000000000000100100000010010; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b00111100000000100001000000000000; MEM_WriteReg = 5'b00010; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b01001; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00010000000000000000000000000000; PCOut = 32'b00000000000000000000001000001000; CPUDataIn = 32'b00000000000000000000000000000001; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00010000000000000000000000000000; CLK = 1'b1; Reg8 = 32'b11111111111111111111111111111111; #20000; //5530000 CLK = 1'b0; #20000; //5550000 WB_Inst = 32'b00111100000000100001000000000000; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; WB_WriteReg = 5'b00010; WB_CPUDataIn = 32'b00000000000000000000000000000001; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00010000000000000000000000000000; Inst = 32'b00100000010111110000000000100000; PCOut = 32'b00000000000000000000001000001100; CPUDataIn = 32'b00000000000000000000000000000000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg9 = 32'b11111111111111111111111111111111; #20000; //5570000 CLK = 1'b0; #20000; //5590000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b00100000010111110000000000100000; WB_WriteReg = 5'b00000; WB_CPUDataIn = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b10000000010000110000000000000000; PCOut = 32'b00000000000000000000001000010000; CLK = 1'b1; Reg2 = 32'b00010000000000000000000000000000; #20000; //5610000 CLK = 1'b0; #20000; //5630000 ID_Inst = 32'b10000000010000110000000000000000; EX_Inst = 32'b00100000010111110000000000100000; EX_WriteReg = 5'b11111; Inst = 32'b10000000010001000000000000000001; PCOut = 32'b00000000000000000000001000010100; CLK = 1'b1; #20000; //5650000 CLK = 1'b0; #20000; //5670000 ID_Inst = 32'b10000000010001000000000000000001; EX_Inst = 32'b10000000010000110000000000000000; MEM_Inst = 32'b00100000010111110000000000100000; MEM_WriteReg = 5'b11111; EX_WriteReg = 5'b00011; MEM_ALUOut = 32'b00010000000000000000000000100000; Inst = 32'b10000000010001010000000000000010; PCOut = 32'b00000000000000000000001000011000; CPUDataIn = 32'b000000000000000000000000XXXXXXXX; ALUOut = 32'b00010000000000000000000000100000; CLK = 1'b1; #20000; //5690000 CLK = 1'b0; #20000; //5710000 WB_Inst = 32'b00100000010111110000000000100000; ID_Inst = 32'b10000000010001010000000000000010; EX_Inst = 32'b10000000010001000000000000000001; MEM_Inst = 32'b10000000010000110000000000000000; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b11111; WB_CPUDataIn = 32'b000000000000000000000000XXXXXXXX; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00010000000000000000000000000000; WB_ALUOut = 32'b00010000000000000000000000100000; SignedLoad = 1'b1; Inst = 32'b10000000010001100000000000000011; PCOut = 32'b00000000000000000000001000011100; CPUDataIn = 32'b00000000000000000000000000000001; CPUDataOut = 32'b11111111111111111111111111111111; MemSize = 2'b01; ALUOut = 32'b00010000000000000000000000000000; CLK = 1'b1; #20000; //5730000 CLK = 1'b0; #20000; //5750000 WB_Inst = 32'b10000000010000110000000000000000; ID_Inst = 32'b10000000010001100000000000000011; EX_Inst = 32'b10000000010001010000000000000010; MEM_Inst = 32'b10000000010001000000000000000001; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00011; WB_CPUDataIn = 32'b00000000000000000000000000000001; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00010000000000000000000000000001; WB_ALUOut = 32'b00010000000000000000000000000000; Inst = 32'b10000000010001110000000000000100; PCOut = 32'b00000000000000000000001000100000; CPUDataIn = 32'b11111111111111111111111111111111; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00010000000000000000000000000001; CLK = 1'b1; Reg31 = 32'b00010000000000000000000000100000; #20000; //5770000 CLK = 1'b0; #20000; //5790000 WB_Inst = 32'b10000000010001000000000000000001; ID_Inst = 32'b10000000010001110000000000000100; EX_Inst = 32'b10000000010001100000000000000011; MEM_Inst = 32'b10000000010001010000000000000010; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_CPUDataIn = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00010000000000000000000000000010; WB_ALUOut = 32'b00010000000000000000000000000001; Inst = 32'b10000011111010001111111111101000; PCOut = 32'b00000000000000000000001000100100; CPUDataIn = 32'b00000000000000000000000000000000; ALUOut = 32'b00010000000000000000000000000010; CLK = 1'b1; Reg3 = 32'b00000000000000000000000000000001; #20000; //5810000 CLK = 1'b0; #20000; //5830000 WB_Inst = 32'b10000000010001010000000000000010; ID_Inst = 32'b10000011111010001111111111101000; EX_Inst = 32'b10000000010001110000000000000100; MEM_Inst = 32'b10000000010001100000000000000011; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; WB_CPUDataIn = 32'b00000000000000000000000000000000; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00010000000000000000000000000011; WB_ALUOut = 32'b00010000000000000000000000000010; Inst = 32'b10000011111010011111111111101011; PCOut = 32'b00000000000000000000001000101000; CPUDataIn = 32'b11111111111111111111111110000000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00010000000000000000000000000011; CLK = 1'b1; Reg4 = 32'b11111111111111111111111111111111; #20000; //5850000 CLK = 1'b0; #20000; //5870000 WB_Inst = 32'b10000000010001100000000000000011; ID_Inst = 32'b10000011111010011111111111101011; EX_Inst = 32'b10000011111010001111111111101000; MEM_Inst = 32'b10000000010001110000000000000100; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00110; WB_CPUDataIn = 32'b11111111111111111111111110000000; MEM_ALUOut = 32'b00010000000000000000000000000100; WB_ALUOut = 32'b00010000000000000000000000000011; Inst = 32'b10100000010000110000000000001100; PCOut = 32'b00000000000000000000001000101100; CPUDataIn = 32'b00000000000000000000000000010000; ALUOut = 32'b00010000000000000000000000000100; CLK = 1'b1; #20000; //5890000 CLK = 1'b0; #20000; //5910000 WB_Inst = 32'b10000000010001110000000000000100; ID_Inst = 32'b10100000010000110000000000001100; EX_Inst = 32'b10000011111010011111111111101011; MEM_Inst = 32'b10000011111010001111111111101000; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; WB_CPUDataIn = 32'b00000000000000000000000000010000; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00010000000000000000000000001000; WB_ALUOut = 32'b00010000000000000000000000000100; Inst = 32'b10100000010001000000000000001101; PCOut = 32'b00000000000000000000001000110000; CPUDataIn = 32'b11111111111111111111111110011000; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00010000000000000000000000001000; CLK = 1'b1; Reg6 = 32'b11111111111111111111111110000000; #20000; //5930000 CLK = 1'b0; #20000; //5950000 WB_Inst = 32'b10000011111010001111111111101000; ID_Inst = 32'b10100000010001000000000000001101; EX_Inst = 32'b10100000010000110000000000001100; MEM_Inst = 32'b10000011111010011111111111101011; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00011; WB_WriteReg = 5'b01000; WB_CPUDataIn = 32'b11111111111111111111111110011000; MEM_ALUOut = 32'b00010000000000000000000000001011; WB_ALUOut = 32'b00010000000000000000000000001000; Inst = 32'b10100000010001010000000000001110; PCOut = 32'b00000000000000000000001000110100; CPUDataIn = 32'b11111111111111111111111111111110; ALUOut = 32'b00010000000000000000000000001011; CLK = 1'b1; Reg7 = 32'b00000000000000000000000000010000; #20000; //5970000 CLK = 1'b0; #20000; //5990000 WB_Inst = 32'b10000011111010011111111111101011; ID_Inst = 32'b10100000010001010000000000001110; EX_Inst = 32'b10100000010001000000000000001101; MEM_Inst = 32'b10100000010000110000000000001100; MEM_RegWrite = 1'b0; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01001; WB_CPUDataIn = 32'b11111111111111111111111111111110; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00010000000000000000000000001100; WB_ALUOut = 32'b00010000000000000000000000001011; SignedLoad = 1'b0; Store = 1'b1; Inst = 32'b10100000010001100000000000001111; PCOut = 32'b00000000000000000000001000111000; CPUDataIn = 32'b000000000000000000000000XXXXXXXX; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00010000000000000000000000001100; CLK = 1'b1; Reg8 = 32'b11111111111111111111111110011000; #20000; //6010000 CLK = 1'b0; #20000; //6030000 WB_Inst = 32'b10100000010000110000000000001100; ID_Inst = 32'b10100000010001100000000000001111; EX_Inst = 32'b10100000010001010000000000001110; MEM_Inst = 32'b10100000010001000000000000001101; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00011; WB_CPUDataIn = 32'b000000000000000000000000XXXXXXXX; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00010000000000000000000000001101; WB_ALUOut = 32'b00010000000000000000000000001100; Inst = 32'b10100000010001110000000000010000; PCOut = 32'b00000000000000000000001000111100; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00010000000000000000000000001101; CLK = 1'b1; Reg9 = 32'b11111111111111111111111111111110; #20000; //6050000 CLK = 1'b0; #20000; //6070000 WB_Inst = 32'b10100000010001000000000000001101; ID_Inst = 32'b10100000010001110000000000010000; EX_Inst = 32'b10100000010001100000000000001111; MEM_Inst = 32'b10100000010001010000000000001110; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00010000000000000000000000001110; WB_ALUOut = 32'b00010000000000000000000000001101; Inst = 32'b10100011111010001111111111110100; PCOut = 32'b00000000000000000000001001000000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00010000000000000000000000001110; CLK = 1'b1; #20000; //6090000 CLK = 1'b0; #20000; //6110000 WB_Inst = 32'b10100000010001010000000000001110; ID_Inst = 32'b10100011111010001111111111110100; EX_Inst = 32'b10100000010001110000000000010000; MEM_Inst = 32'b10100000010001100000000000001111; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; MEM_CPUDataOut = 32'b11111111111111111111111110000000; MEM_ALUOut = 32'b00010000000000000000000000001111; WB_ALUOut = 32'b00010000000000000000000000001110; Inst = 32'b10100011111010011111111111110111; PCOut = 32'b00000000000000000000001001000100; CPUDataOut = 32'b11111111111111111111111110000000; ALUOut = 32'b00010000000000000000000000001111; CLK = 1'b1; #20000; //6130000 CLK = 1'b0; #20000; //6150000 WB_Inst = 32'b10100000010001100000000000001111; ID_Inst = 32'b10100011111010011111111111110111; EX_Inst = 32'b10100011111010001111111111110100; MEM_Inst = 32'b10100000010001110000000000010000; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00110; MEM_CPUDataOut = 32'b00000000000000000000000000010000; MEM_ALUOut = 32'b00010000000000000000000000010000; WB_ALUOut = 32'b00010000000000000000000000001111; Inst = 32'b10010000010000110000000000001100; PCOut = 32'b00000000000000000000001001001000; CPUDataIn = 32'b000000000000000000000000XXXXXXXX; CPUDataOut = 32'b00000000000000000000000000010000; ALUOut = 32'b00010000000000000000000000010000; CLK = 1'b1; #20000; //6170000 CLK = 1'b0; #20000; //6190000 WB_Inst = 32'b10100000010001110000000000010000; ID_Inst = 32'b10010000010000110000000000001100; EX_Inst = 32'b10100011111010011111111111110111; MEM_Inst = 32'b10100011111010001111111111110100; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; MEM_CPUDataOut = 32'b11111111111111111111111110011000; MEM_ALUOut = 32'b00010000000000000000000000010100; WB_ALUOut = 32'b00010000000000000000000000010000; Inst = 32'b10010000010001000000000000001101; PCOut = 32'b00000000000000000000001001001100; CPUDataOut = 32'b11111111111111111111111110011000; ALUOut = 32'b00010000000000000000000000010100; CLK = 1'b1; #20000; //6210000 CLK = 1'b0; #20000; //6230000 WB_Inst = 32'b10100011111010001111111111110100; ID_Inst = 32'b10010000010001000000000000001101; EX_Inst = 32'b10010000010000110000000000001100; MEM_Inst = 32'b10100011111010011111111111110111; EX_RegWrite = 1'b1; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00011; WB_WriteReg = 5'b01000; MEM_CPUDataOut = 32'b11111111111111111111111111111110; MEM_ALUOut = 32'b00010000000000000000000000010111; WB_ALUOut = 32'b00010000000000000000000000010100; Inst = 32'b10010000010001010000000000001110; PCOut = 32'b00000000000000000000001001010000; CPUDataOut = 32'b11111111111111111111111111111110; ALUOut = 32'b00010000000000000000000000010111; CLK = 1'b1; #20000; //6250000 CLK = 1'b0; #20000; //6270000 WB_Inst = 32'b10100011111010011111111111110111; ID_Inst = 32'b10010000010001010000000000001110; EX_Inst = 32'b10010000010001000000000000001101; MEM_Inst = 32'b10010000010000110000000000001100; MEM_RegWrite = 1'b1; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01001; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00010000000000000000000000001100; WB_ALUOut = 32'b00010000000000000000000000010111; Store = 1'b0; Inst = 32'b10010000010001100000000000001111; PCOut = 32'b00000000000000000000001001010100; CPUDataIn = 32'b00000000000000000000000000000001; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00010000000000000000000000001100; CLK = 1'b1; #20000; //6290000 CLK = 1'b0; #20000; //6310000 WB_Inst = 32'b10010000010000110000000000001100; ID_Inst = 32'b10010000010001100000000000001111; EX_Inst = 32'b10010000010001010000000000001110; MEM_Inst = 32'b10010000010001000000000000001101; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_RegWrite = 1'b1; WB_WriteReg = 5'b00011; WB_CPUDataIn = 32'b00000000000000000000000000000001; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00010000000000000000000000001101; WB_ALUOut = 32'b00010000000000000000000000001100; Inst = 32'b10010000010001110000000000010000; PCOut = 32'b00000000000000000000001001011000; CPUDataIn = 32'b00000000000000000000000011111111; CPUDataOut = 32'b11111111111111111111111111111111; ALUOut = 32'b00010000000000000000000000001101; CLK = 1'b1; #20000; //6330000 CLK = 1'b0; #20000; //6350000 WB_Inst = 32'b10010000010001000000000000001101; ID_Inst = 32'b10010000010001110000000000010000; EX_Inst = 32'b10010000010001100000000000001111; MEM_Inst = 32'b10010000010001010000000000001110; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_CPUDataIn = 32'b00000000000000000000000011111111; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00010000000000000000000000001110; WB_ALUOut = 32'b00010000000000000000000000001101; Inst = 32'b10010011111010001111111111110100; PCOut = 32'b00000000000000000000001001011100; CPUDataIn = 32'b00000000000000000000000000000000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00010000000000000000000000001110; CLK = 1'b1; #20000; //6370000 CLK = 1'b0; #20000; //6390000 WB_Inst = 32'b10010000010001010000000000001110; ID_Inst = 32'b10010011111010001111111111110100; EX_Inst = 32'b10010000010001110000000000010000; MEM_Inst = 32'b10010000010001100000000000001111; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; WB_CPUDataIn = 32'b00000000000000000000000000000000; MEM_CPUDataOut = 32'b11111111111111111111111110000000; MEM_ALUOut = 32'b00010000000000000000000000001111; WB_ALUOut = 32'b00010000000000000000000000001110; Inst = 32'b10010011111010011111111111110111; PCOut = 32'b00000000000000000000001001100000; CPUDataIn = 32'b00000000000000000000000010000000; CPUDataOut = 32'b11111111111111111111111110000000; ALUOut = 32'b00010000000000000000000000001111; CLK = 1'b1; Reg4 = 32'b00000000000000000000000011111111; #20000; //6410000 CLK = 1'b0; #20000; //6430000 WB_Inst = 32'b10010000010001100000000000001111; ID_Inst = 32'b10010011111010011111111111110111; EX_Inst = 32'b10010011111010001111111111110100; MEM_Inst = 32'b10010000010001110000000000010000; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00110; WB_CPUDataIn = 32'b00000000000000000000000010000000; MEM_CPUDataOut = 32'b00000000000000000000000000010000; MEM_ALUOut = 32'b00010000000000000000000000010000; WB_ALUOut = 32'b00010000000000000000000000001111; Inst = 32'b10000111111000111111111111100000; PCOut = 32'b00000000000000000000001001100100; CPUDataIn = 32'b00000000000000000000000000010000; CPUDataOut = 32'b00000000000000000000000000010000; ALUOut = 32'b00010000000000000000000000010000; CLK = 1'b1; #20000; //6450000 CLK = 1'b0; #20000; //6470000 WB_Inst = 32'b10010000010001110000000000010000; ID_Inst = 32'b10000111111000111111111111100000; EX_Inst = 32'b10010011111010011111111111110111; MEM_Inst = 32'b10010011111010001111111111110100; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b01001; WB_WriteReg = 5'b00111; WB_CPUDataIn = 32'b00000000000000000000000000010000; MEM_CPUDataOut = 32'b11111111111111111111111110011000; MEM_ALUOut = 32'b00010000000000000000000000010100; WB_ALUOut = 32'b00010000000000000000000000010000; Inst = 32'b10000100010001000000000000000010; PCOut = 32'b00000000000000000000001001101000; CPUDataIn = 32'b00000000000000000000000010011000; CPUDataOut = 32'b11111111111111111111111110011000; ALUOut = 32'b00010000000000000000000000010100; CLK = 1'b1; Reg6 = 32'b00000000000000000000000010000000; #20000; //6490000 CLK = 1'b0; #20000; //6510000 WB_Inst = 32'b10010011111010001111111111110100; ID_Inst = 32'b10000100010001000000000000000010; EX_Inst = 32'b10000111111000111111111111100000; MEM_Inst = 32'b10010011111010011111111111110111; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00011; WB_WriteReg = 5'b01000; WB_CPUDataIn = 32'b00000000000000000000000010011000; MEM_CPUDataOut = 32'b11111111111111111111111111111110; MEM_ALUOut = 32'b00010000000000000000000000010111; WB_ALUOut = 32'b00010000000000000000000000010100; Inst = 32'b10000111111001011111111111100100; PCOut = 32'b00000000000000000000001001101100; CPUDataIn = 32'b00000000000000000000000011111110; CPUDataOut = 32'b11111111111111111111111111111110; ALUOut = 32'b00010000000000000000000000010111; CLK = 1'b1; #20000; //6530000 CLK = 1'b0; #20000; //6550000 WB_Inst = 32'b10010011111010011111111111110111; ID_Inst = 32'b10000111111001011111111111100100; EX_Inst = 32'b10000100010001000000000000000010; MEM_Inst = 32'b10000111111000111111111111100000; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b01001; WB_CPUDataIn = 32'b00000000000000000000000011111110; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00010000000000000000000000000000; WB_ALUOut = 32'b00010000000000000000000000010111; SignedLoad = 1'b1; Inst = 32'b10000100010001100000000000000110; PCOut = 32'b00000000000000000000001001110000; CPUDataIn = 32'b11111111111111111111111100000001; CPUDataOut = 32'b00000000000000000000000000000001; MemSize = 2'b10; ALUOut = 32'b00010000000000000000000000000000; CLK = 1'b1; Reg8 = 32'b00000000000000000000000010011000; #20000; //6570000 CLK = 1'b0; #20000; //6590000 WB_Inst = 32'b10000111111000111111111111100000; ID_Inst = 32'b10000100010001100000000000000110; EX_Inst = 32'b10000111111001011111111111100100; MEM_Inst = 32'b10000100010001000000000000000010; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_WriteReg = 5'b00011; WB_CPUDataIn = 32'b11111111111111111111111100000001; MEM_CPUDataOut = 32'b00000000000000000000000011111111; MEM_ALUOut = 32'b00010000000000000000000000000010; WB_ALUOut = 32'b00010000000000000000000000000000; Inst = 32'b10100111111000111111111111101100; PCOut = 32'b00000000000000000000001001110100; CPUDataIn = 32'b11111111111111111000000000000000; CPUDataOut = 32'b00000000000000000000000011111111; ALUOut = 32'b00010000000000000000000000000010; CLK = 1'b1; Reg9 = 32'b00000000000000000000000011111110; #20000; //6610000 CLK = 1'b0; #20000; //6630000 WB_Inst = 32'b10000100010001000000000000000010; ID_Inst = 32'b10100111111000111111111111101100; EX_Inst = 32'b10000100010001100000000000000110; MEM_Inst = 32'b10000111111001011111111111100100; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_CPUDataIn = 32'b11111111111111111000000000000000; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00010000000000000000000000000100; WB_ALUOut = 32'b00010000000000000000000000000010; Inst = 32'b10100100010001000000000000001110; PCOut = 32'b00000000000000000000001001111000; CPUDataIn = 32'b00000000000000000011001000010000; CPUDataOut = 32'b00000000000000000000000000000000; ALUOut = 32'b00010000000000000000000000000100; CLK = 1'b1; Reg3 = 32'b11111111111111111111111100000001; #20000; //6650000 CLK = 1'b0; #20000; //6670000 WB_Inst = 32'b10000111111001011111111111100100; ID_Inst = 32'b10100100010001000000000000001110; EX_Inst = 32'b10100111111000111111111111101100; MEM_Inst = 32'b10000100010001100000000000000110; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00011; WB_WriteReg = 5'b00101; WB_CPUDataIn = 32'b00000000000000000011001000010000; MEM_CPUDataOut = 32'b00000000000000000000000010000000; MEM_ALUOut = 32'b00010000000000000000000000000110; WB_ALUOut = 32'b00010000000000000000000000000100; Inst = 32'b10100111111001011111111111110000; PCOut = 32'b00000000000000000000001001111100; CPUDataIn = 32'b00000000000000000111011001010100; CPUDataOut = 32'b00000000000000000000000010000000; ALUOut = 32'b00010000000000000000000000000110; CLK = 1'b1; Reg4 = 32'b11111111111111111000000000000000; #20000; //6690000 CLK = 1'b0; #20000; //6710000 WB_Inst = 32'b10000100010001100000000000000110; ID_Inst = 32'b10100111111001011111111111110000; EX_Inst = 32'b10100100010001000000000000001110; MEM_Inst = 32'b10100111111000111111111111101100; MEM_RegWrite = 1'b0; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; WB_CPUDataIn = 32'b00000000000000000111011001010100; MEM_CPUDataOut = 32'b11111111111111111111111100000001; MEM_ALUOut = 32'b00010000000000000000000000001100; WB_ALUOut = 32'b00010000000000000000000000000110; SignedLoad = 1'b0; Store = 1'b1; Inst = 32'b10100100010001100000000000010010; PCOut = 32'b00000000000000000000001010000000; CPUDataIn = 32'b00000000000000001111111100000001; CPUDataOut = 32'b11111111111111111111111100000001; ALUOut = 32'b00010000000000000000000000001100; CLK = 1'b1; Reg5 = 32'b00000000000000000011001000010000; #20000; //6730000 CLK = 1'b0; #20000; //6750000 WB_Inst = 32'b10100111111000111111111111101100; ID_Inst = 32'b10100100010001100000000000010010; EX_Inst = 32'b10100111111001011111111111110000; MEM_Inst = 32'b10100100010001000000000000001110; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00011; WB_CPUDataIn = 32'b00000000000000001111111100000001; MEM_CPUDataOut = 32'b11111111111111111000000000000000; MEM_ALUOut = 32'b00010000000000000000000000001110; WB_ALUOut = 32'b00010000000000000000000000001100; Inst = 32'b10010100010000110000000000001100; PCOut = 32'b00000000000000000000001010000100; CPUDataIn = 32'b00000000000000001000000000000000; CPUDataOut = 32'b11111111111111111000000000000000; ALUOut = 32'b00010000000000000000000000001110; CLK = 1'b1; Reg6 = 32'b00000000000000000111011001010100; #20000; //6770000 CLK = 1'b0; #20000; //6790000 WB_Inst = 32'b10100100010001000000000000001110; ID_Inst = 32'b10010100010000110000000000001100; EX_Inst = 32'b10100100010001100000000000010010; MEM_Inst = 32'b10100111111001011111111111110000; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_CPUDataIn = 32'b00000000000000001000000000000000; MEM_CPUDataOut = 32'b00000000000000000011001000010000; MEM_ALUOut = 32'b00010000000000000000000000010000; WB_ALUOut = 32'b00010000000000000000000000001110; Inst = 32'b10010111111001001111111111101110; PCOut = 32'b00000000000000000000001010001000; CPUDataIn = 32'b0000000000000000XXXXXXXX00010000; CPUDataOut = 32'b00000000000000000011001000010000; ALUOut = 32'b00010000000000000000000000010000; CLK = 1'b1; #20000; //6810000 CLK = 1'b0; #20000; //6830000 WB_Inst = 32'b10100111111001011111111111110000; ID_Inst = 32'b10010111111001001111111111101110; EX_Inst = 32'b10010100010000110000000000001100; MEM_Inst = 32'b10100100010001100000000000010010; EX_RegWrite = 1'b1; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00011; WB_WriteReg = 5'b00101; WB_CPUDataIn = 32'b0000000000000000XXXXXXXX00010000; MEM_CPUDataOut = 32'b00000000000000000111011001010100; MEM_ALUOut = 32'b00010000000000000000000000010010; WB_ALUOut = 32'b00010000000000000000000000010000; Inst = 32'b10010100010001010000000000010000; PCOut = 32'b00000000000000000000001010001100; CPUDataIn = 32'b0000000000000000XXXXXXXXXXXXXXXX; CPUDataOut = 32'b00000000000000000111011001010100; ALUOut = 32'b00010000000000000000000000010010; CLK = 1'b1; #20000; //6850000 CLK = 1'b0; #20000; //6870000 WB_Inst = 32'b10100100010001100000000000010010; ID_Inst = 32'b10010100010001010000000000010000; EX_Inst = 32'b10010111111001001111111111101110; MEM_Inst = 32'b10010100010000110000000000001100; MEM_RegWrite = 1'b1; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b00100; WB_WriteReg = 5'b00110; WB_CPUDataIn = 32'b0000000000000000XXXXXXXXXXXXXXXX; MEM_CPUDataOut = 32'b11111111111111111111111100000001; MEM_ALUOut = 32'b00010000000000000000000000001100; WB_ALUOut = 32'b00010000000000000000000000010010; Store = 1'b0; Inst = 32'b10010111111001101111111111110010; PCOut = 32'b00000000000000000000001010010000; CPUDataIn = 32'b00000000000000001111111100000001; CPUDataOut = 32'b11111111111111111111111100000001; ALUOut = 32'b00010000000000000000000000001100; CLK = 1'b1; #20000; //6890000 CLK = 1'b0; #20000; //6910000 WB_Inst = 32'b10010100010000110000000000001100; ID_Inst = 32'b10010111111001101111111111110010; EX_Inst = 32'b10010100010001010000000000010000; MEM_Inst = 32'b10010111111001001111111111101110; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b00101; WB_RegWrite = 1'b1; WB_WriteReg = 5'b00011; WB_CPUDataIn = 32'b00000000000000001111111100000001; MEM_CPUDataOut = 32'b11111111111111111000000000000000; MEM_ALUOut = 32'b00010000000000000000000000001110; WB_ALUOut = 32'b00010000000000000000000000001100; Inst = 32'b10001100010001110000000000000000; PCOut = 32'b00000000000000000000001010010100; CPUDataIn = 32'b00000000000000001000000000000000; CPUDataOut = 32'b11111111111111111000000000000000; ALUOut = 32'b00010000000000000000000000001110; CLK = 1'b1; #20000; //6930000 CLK = 1'b0; #20000; //6950000 WB_Inst = 32'b10010111111001001111111111101110; ID_Inst = 32'b10001100010001110000000000000000; EX_Inst = 32'b10010111111001101111111111110010; MEM_Inst = 32'b10010100010001010000000000010000; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00110; WB_WriteReg = 5'b00100; WB_CPUDataIn = 32'b00000000000000001000000000000000; MEM_CPUDataOut = 32'b00000000000000000011001000010000; MEM_ALUOut = 32'b00010000000000000000000000010000; WB_ALUOut = 32'b00010000000000000000000000001110; Inst = 32'b10101100010000110000000000001100; PCOut = 32'b00000000000000000000001010011000; CPUDataIn = 32'b00000000000000000011001000010000; CPUDataOut = 32'b00000000000000000011001000010000; ALUOut = 32'b00010000000000000000000000010000; CLK = 1'b1; Reg3 = 32'b00000000000000001111111100000001; #20000; //6970000 CLK = 1'b0; #20000; //6990000 WB_Inst = 32'b10010100010001010000000000010000; ID_Inst = 32'b10101100010000110000000000001100; EX_Inst = 32'b10001100010001110000000000000000; MEM_Inst = 32'b10010111111001101111111111110010; MEM_WriteReg = 5'b00110; EX_WriteReg = 5'b00111; WB_WriteReg = 5'b00101; WB_CPUDataIn = 32'b00000000000000000011001000010000; MEM_CPUDataOut = 32'b00000000000000000111011001010100; MEM_ALUOut = 32'b00010000000000000000000000010010; WB_ALUOut = 32'b00010000000000000000000000010000; Inst = 32'b10001111111010001111111111100100; PCOut = 32'b00000000000000000000001010011100; CPUDataIn = 32'b00000000000000000111011001010100; CPUDataOut = 32'b00000000000000000111011001010100; ALUOut = 32'b00010000000000000000000000010010; CLK = 1'b1; Reg4 = 32'b00000000000000001000000000000000; #20000; //7010000 CLK = 1'b0; #20000; //7030000 WB_Inst = 32'b10010111111001101111111111110010; ID_Inst = 32'b10001111111010001111111111100100; EX_Inst = 32'b10101100010000110000000000001100; MEM_Inst = 32'b10001100010001110000000000000000; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b00111; EX_WriteReg = 5'b00011; WB_WriteReg = 5'b00110; WB_CPUDataIn = 32'b00000000000000000111011001010100; MEM_CPUDataOut = 32'b00000000000000000000000000010000; MEM_ALUOut = 32'b00010000000000000000000000000000; WB_ALUOut = 32'b00010000000000000000000000010010; Inst = 32'b10101111111001001111111111110000; PCOut = 32'b00000000000000000000001010100000; CPUDataIn = 32'b10000000000000001111111100000001; CPUDataOut = 32'b00000000000000000000000000010000; MemSize = 2'b11; ALUOut = 32'b00010000000000000000000000000000; CLK = 1'b1; #20000; //7050000 CLK = 1'b0; #20000; //7070000 WB_Inst = 32'b10001100010001110000000000000000; ID_Inst = 32'b10101111111001001111111111110000; EX_Inst = 32'b10001111111010001111111111100100; MEM_Inst = 32'b10101100010000110000000000001100; MEM_RegWrite = 1'b0; EX_RegWrite = 1'b1; MEM_WriteReg = 5'b00011; EX_WriteReg = 5'b01000; WB_WriteReg = 5'b00111; WB_CPUDataIn = 32'b10000000000000001111111100000001; MEM_CPUDataOut = 32'b00000000000000001111111100000001; MEM_ALUOut = 32'b00010000000000000000000000001100; WB_ALUOut = 32'b00010000000000000000000000000000; Store = 1'b1; Inst = 32'b10001100010010010000000000001000; PCOut = 32'b00000000000000000000001010100100; CPUDataOut = 32'b00000000000000001111111100000001; ALUOut = 32'b00010000000000000000000000001100; CLK = 1'b1; #20000; //7090000 CLK = 1'b0; #20000; //7110000 WB_Inst = 32'b10101100010000110000000000001100; ID_Inst = 32'b10001100010010010000000000001000; EX_Inst = 32'b10101111111001001111111111110000; MEM_Inst = 32'b10001111111010001111111111100100; MEM_RegWrite = 1'b1; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b01000; EX_WriteReg = 5'b00100; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00011; MEM_CPUDataOut = 32'b00000000000000000000000010011000; MEM_ALUOut = 32'b00010000000000000000000000000100; WB_ALUOut = 32'b00010000000000000000000000001100; Store = 1'b0; Inst = 32'b10101100010001010000000000010100; PCOut = 32'b00000000000000000000001010101000; CPUDataIn = 32'b01110110010101000011001000010000; CPUDataOut = 32'b00000000000000000000000010011000; ALUOut = 32'b00010000000000000000000000000100; CLK = 1'b1; Reg7 = 32'b10000000000000001111111100000001; #20000; //7130000 CLK = 1'b0; #20000; //7150000 WB_Inst = 32'b10001111111010001111111111100100; ID_Inst = 32'b10101100010001010000000000010100; EX_Inst = 32'b10001100010010010000000000001000; MEM_Inst = 32'b10101111111001001111111111110000; MEM_RegWrite = 1'b0; EX_RegWrite = 1'b1; MEM_WriteReg = 5'b00100; EX_WriteReg = 5'b01001; WB_RegWrite = 1'b1; WB_WriteReg = 5'b01000; WB_CPUDataIn = 32'b01110110010101000011001000010000; MEM_CPUDataOut = 32'b00000000000000001000000000000000; MEM_ALUOut = 32'b00010000000000000000000000010000; WB_ALUOut = 32'b00010000000000000000000000000100; Store = 1'b1; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000001010101100; CPUDataOut = 32'b00000000000000001000000000000000; ALUOut = 32'b00010000000000000000000000010000; CLK = 1'b1; #20000; //7170000 CLK = 1'b0; #20000; //7190000 WB_Inst = 32'b10101111111001001111111111110000; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b10101100010001010000000000010100; MEM_Inst = 32'b10001100010010010000000000001000; MEM_RegWrite = 1'b1; EX_RegWrite = 1'b0; MEM_WriteReg = 5'b01001; EX_WriteReg = 5'b00101; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00100; MEM_CPUDataOut = 32'b00000000000000000000000011111110; MEM_ALUOut = 32'b00010000000000000000000000001000; WB_ALUOut = 32'b00010000000000000000000000010000; Store = 1'b0; Inst = 32'b10001111111010101111111111101100; PCOut = 32'b00000000000000000000001010110000; CPUDataIn = 32'b11111110110111001011101010011000; CPUDataOut = 32'b00000000000000000000000011111110; ALUOut = 32'b00010000000000000000000000001000; CLK = 1'b1; Reg8 = 32'b01110110010101000011001000010000; #20000; //7210000 CLK = 1'b0; #20000; //7230000 WB_Inst = 32'b10001100010010010000000000001000; ID_Inst = 32'b10001111111010101111111111101100; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b10101100010001010000000000010100; MEM_RegWrite = 1'b0; EX_RegWrite = 1'b1; MEM_WriteReg = 5'b00101; EX_WriteReg = 5'b00000; WB_RegWrite = 1'b1; WB_WriteReg = 5'b01001; WB_CPUDataIn = 32'b11111110110111001011101010011000; MEM_CPUDataOut = 32'b00000000000000000011001000010000; MEM_ALUOut = 32'b00010000000000000000000000010100; WB_ALUOut = 32'b00010000000000000000000000001000; Store = 1'b1; Inst = 32'b10001100010010110000000000010000; PCOut = 32'b00000000000000000000001010110100; CPUDataIn = 32'b11111110XXXXXXXXXXXXXXXX10011000; CPUDataOut = 32'b00000000000000000011001000010000; ALUOut = 32'b00010000000000000000000000010100; CLK = 1'b1; #20000; //7250000 CLK = 1'b0; #20000; //7270000 WB_Inst = 32'b10101100010001010000000000010100; ID_Inst = 32'b10001100010010110000000000010000; EX_Inst = 32'b10001111111010101111111111101100; MEM_Inst = 32'b00000000000000000000000000000000; MEM_RegWrite = 1'b1; MEM_WriteReg = 5'b00000; EX_WriteReg = 5'b01010; WB_RegWrite = 1'b0; WB_WriteReg = 5'b00101; WB_CPUDataIn = 32'b11111110XXXXXXXXXXXXXXXX10011000; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00010000000000000000000000010100; Store = 1'b0; Inst = 32'b10001111111011001111111111110100; PCOut = 32'b00000000000000000000001010111000; CPUDataIn = 32'b00000000000000000000000000000000; CPUDataOut = 32'b00000000000000000000000000000000; MemSize = 2'b00; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg9 = 32'b11111110110111001011101010011000; #20000; //7290000 CLK = 1'b0; #20000; //7310000 WB_Inst = 32'b00000000000000000000000000000000; ID_Inst = 32'b10001111111011001111111111110100; EX_Inst = 32'b10001100010010110000000000010000; MEM_Inst = 32'b10001111111010101111111111101100; MEM_WriteReg = 5'b01010; EX_WriteReg = 5'b01011; WB_RegWrite = 1'b1; WB_WriteReg = 5'b00000; WB_CPUDataIn = 32'b00000000000000000000000000000000; MEM_CPUDataOut = 32'b11111111111111111111111111111111; MEM_ALUOut = 32'b00010000000000000000000000001100; WB_ALUOut = 32'b00000000000000000000000000000000; Inst = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000001010111100; CPUDataIn = 32'b00000000000000001111111100000001; CPUDataOut = 32'b11111111111111111111111111111111; MemSize = 2'b11; ALUOut = 32'b00010000000000000000000000001100; CLK = 1'b1; #20000; //7330000 CLK = 1'b0; #20000; //7350000 WB_Inst = 32'b10001111111010101111111111101100; ID_Inst = 32'b00000000000000000000000000000000; EX_Inst = 32'b10001111111011001111111111110100; MEM_Inst = 32'b10001100010010110000000000010000; MEM_WriteReg = 5'b01011; EX_WriteReg = 5'b01100; WB_WriteReg = 5'b01010; WB_CPUDataIn = 32'b00000000000000001111111100000001; MEM_CPUDataOut = 32'b00000000000000000000000000000001; MEM_ALUOut = 32'b00010000000000000000000000010000; WB_ALUOut = 32'b00010000000000000000000000001100; PCOut = 32'b00000000000000000000001011000000; CPUDataIn = 32'b00000000000000001000000000000000; CPUDataOut = 32'b00000000000000000000000000000001; ALUOut = 32'b00010000000000000000000000010000; CLK = 1'b1; #20000; //7370000 CLK = 1'b0; #20000; //7390000 WB_Inst = 32'b10001100010010110000000000010000; EX_Inst = 32'b00000000000000000000000000000000; MEM_Inst = 32'b10001111111011001111111111110100; MEM_WriteReg = 5'b01100; EX_WriteReg = 5'b00000; WB_WriteReg = 5'b01011; WB_CPUDataIn = 32'b00000000000000001000000000000000; MEM_CPUDataOut = 32'b00000000000000000000000000000010; MEM_ALUOut = 32'b00010000000000000000000000010100; WB_ALUOut = 32'b00010000000000000000000000010000; PCOut = 32'b00000000000000000000001011000100; CPUDataIn = 32'b00000000000000000011001000010000; CPUDataOut = 32'b00000000000000000000000000000010; ALUOut = 32'b00010000000000000000000000010100; CLK = 1'b1; Reg10 = 32'b00000000000000001111111100000001; #20000; //7410000 CLK = 1'b0; #20000; //7430000 WB_Inst = 32'b10001111111011001111111111110100; MEM_Inst = 32'b00000000000000000000000000000000; MEM_WriteReg = 5'b00000; WB_WriteReg = 5'b01100; WB_CPUDataIn = 32'b00000000000000000011001000010000; MEM_CPUDataOut = 32'b00000000000000000000000000000000; MEM_ALUOut = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00010000000000000000000000010100; PCOut = 32'b00000000000000000000001011001000; CPUDataIn = 32'b00000000000000000000000000000000; CPUDataOut = 32'b00000000000000000000000000000000; MemSize = 2'b00; ALUOut = 32'b00000000000000000000000000000000; CLK = 1'b1; Reg11 = 32'b00000000000000001000000000000000; #20000; //7450000 CLK = 1'b0; #20000; //7470000 WB_Inst = 32'b00000000000000000000000000000000; WB_WriteReg = 5'b00000; WB_CPUDataIn = 32'b00000000000000000000000000000000; WB_ALUOut = 32'b00000000000000000000000000000000; PCOut = 32'b00000000000000000000001011001100; CLK = 1'b1; Reg12 = 32'b00000000000000000011001000010000; #20000; //7490000 CLK = 1'b0; #20000; //7510000 Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; PCOut = 32'b00000000000000000000001011010000; CLK = 1'b1; end // end of stimulus process //Set of always bloks for ports monitoring. //One block per output port. //Always block for monitoring port "Store"; always @(Store or Store_actual) begin #Store_WaitTime if (compare_Store(Store,Store_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Store: Expected value is %b, Actual value is %b",Store,Store_actual); $display($realtime,,"ps; Error on port Store: Expected value is %b, Actual value is %b",Store,Store_actual); end end //Always block for monitoring port "SignedLoad"; always @(SignedLoad or SignedLoad_actual) begin #SignedLoad_WaitTime if (compare_SignedLoad(SignedLoad,SignedLoad_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port SignedLoad: Expected value is %b, Actual value is %b",SignedLoad,SignedLoad_actual); $display($realtime,,"ps; Error on port SignedLoad: Expected value is %b, Actual value is %b",SignedLoad,SignedLoad_actual); end end //Always block for monitoring port "PCOut"; always @(PCOut or PCOut_actual) begin #PCOut_WaitTime if (compare_PCOut(PCOut,PCOut_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port PCOut: Expected value is %b, Actual value is %b",PCOut,PCOut_actual); $display($realtime,,"ps; Error on port PCOut: Expected value is %b, Actual value is %b",PCOut,PCOut_actual); end end //Always block for monitoring port "MemSize"; always @(MemSize or MemSize_actual) begin #MemSize_WaitTime if (compare_MemSize(MemSize,MemSize_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port MemSize: Expected value is %b, Actual value is %b",MemSize,MemSize_actual); $display($realtime,,"ps; Error on port MemSize: Expected value is %b, Actual value is %b",MemSize,MemSize_actual); end end //Always block for monitoring port "CPUDataOut"; always @(CPUDataOut or CPUDataOut_actual) begin #CPUDataOut_WaitTime if (compare_CPUDataOut(CPUDataOut,CPUDataOut_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port CPUDataOut: Expected value is %b, Actual value is %b",CPUDataOut,CPUDataOut_actual); $display($realtime,,"ps; Error on port CPUDataOut: Expected value is %b, Actual value is %b",CPUDataOut,CPUDataOut_actual); end end //Always block for monitoring port "ALUOut"; always @(ALUOut or ALUOut_actual) begin #ALUOut_WaitTime if (compare_ALUOut(ALUOut,ALUOut_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual); $display($realtime,,"ps; Error on port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual); end end //Always block for monitoring port "ID_Inst"; always @(ID_Inst or ID_Inst_actual) begin #ID_Inst_WaitTime if (compare_ID_Inst(ID_Inst,ID_Inst_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port ID_Inst: Expected value is %b, Actual value is %b",ID_Inst,ID_Inst_actual); $display($realtime,,"ps; Error on port ID_Inst: Expected value is %b, Actual value is %b",ID_Inst,ID_Inst_actual); end end //Always block for monitoring port "EX_Inst"; always @(EX_Inst or EX_Inst_actual) begin #EX_Inst_WaitTime if (compare_EX_Inst(EX_Inst,EX_Inst_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port EX_Inst: Expected value is %b, Actual value is %b",EX_Inst,EX_Inst_actual); $display($realtime,,"ps; Error on port EX_Inst: Expected value is %b, Actual value is %b",EX_Inst,EX_Inst_actual); end end //Always block for monitoring port "MEM_Inst"; always @(MEM_Inst or MEM_Inst_actual) begin #MEM_Inst_WaitTime if (compare_MEM_Inst(MEM_Inst,MEM_Inst_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port MEM_Inst: Expected value is %b, Actual value is %b",MEM_Inst,MEM_Inst_actual); $display($realtime,,"ps; Error on port MEM_Inst: Expected value is %b, Actual value is %b",MEM_Inst,MEM_Inst_actual); end end //Always block for monitoring port "WB_Inst"; always @(WB_Inst or WB_Inst_actual) begin #WB_Inst_WaitTime if (compare_WB_Inst(WB_Inst,WB_Inst_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port WB_Inst: Expected value is %b, Actual value is %b",WB_Inst,WB_Inst_actual); $display($realtime,,"ps; Error on port WB_Inst: Expected value is %b, Actual value is %b",WB_Inst,WB_Inst_actual); end end //Always block for monitoring port "EX_RegWrite"; always @(EX_RegWrite or EX_RegWrite_actual) begin #EX_RegWrite_WaitTime if (compare_EX_RegWrite(EX_RegWrite,EX_RegWrite_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port EX_RegWrite: Expected value is %b, Actual value is %b",EX_RegWrite,EX_RegWrite_actual); $display($realtime,,"ps; Error on port EX_RegWrite: Expected value is %b, Actual value is %b",EX_RegWrite,EX_RegWrite_actual); end end //Always block for monitoring port "MEM_RegWrite"; always @(MEM_RegWrite or MEM_RegWrite_actual) begin #MEM_RegWrite_WaitTime if (compare_MEM_RegWrite(MEM_RegWrite,MEM_RegWrite_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port MEM_RegWrite: Expected value is %b, Actual value is %b",MEM_RegWrite,MEM_RegWrite_actual); $display($realtime,,"ps; Error on port MEM_RegWrite: Expected value is %b, Actual value is %b",MEM_RegWrite,MEM_RegWrite_actual); end end //Always block for monitoring port "WB_RegWrite"; always @(WB_RegWrite or WB_RegWrite_actual) begin #WB_RegWrite_WaitTime if (compare_WB_RegWrite(WB_RegWrite,WB_RegWrite_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port WB_RegWrite: Expected value is %b, Actual value is %b",WB_RegWrite,WB_RegWrite_actual); $display($realtime,,"ps; Error on port WB_RegWrite: Expected value is %b, Actual value is %b",WB_RegWrite,WB_RegWrite_actual); end end //Always block for monitoring port "EX_WriteReg"; always @(EX_WriteReg or EX_WriteReg_actual) begin #EX_WriteReg_WaitTime if (compare_EX_WriteReg(EX_WriteReg,EX_WriteReg_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port EX_WriteReg: Expected value is %b, Actual value is %b",EX_WriteReg,EX_WriteReg_actual); $display($realtime,,"ps; Error on port EX_WriteReg: Expected value is %b, Actual value is %b",EX_WriteReg,EX_WriteReg_actual); end end //Always block for monitoring port "MEM_WriteReg"; always @(MEM_WriteReg or MEM_WriteReg_actual) begin #MEM_WriteReg_WaitTime if (compare_MEM_WriteReg(MEM_WriteReg,MEM_WriteReg_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port MEM_WriteReg: Expected value is %b, Actual value is %b",MEM_WriteReg,MEM_WriteReg_actual); $display($realtime,,"ps; Error on port MEM_WriteReg: Expected value is %b, Actual value is %b",MEM_WriteReg,MEM_WriteReg_actual); end end //Always block for monitoring port "WB_WriteReg"; always @(WB_WriteReg or WB_WriteReg_actual) begin #WB_WriteReg_WaitTime if (compare_WB_WriteReg(WB_WriteReg,WB_WriteReg_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port WB_WriteReg: Expected value is %b, Actual value is %b",WB_WriteReg,WB_WriteReg_actual); $display($realtime,,"ps; Error on port WB_WriteReg: Expected value is %b, Actual value is %b",WB_WriteReg,WB_WriteReg_actual); end end //Always block for monitoring port "WB_CPUDataIn"; always @(WB_CPUDataIn or WB_CPUDataIn_actual) begin #WB_CPUDataIn_WaitTime if (compare_WB_CPUDataIn(WB_CPUDataIn,WB_CPUDataIn_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port WB_CPUDataIn: Expected value is %b, Actual value is %b",WB_CPUDataIn,WB_CPUDataIn_actual); $display($realtime,,"ps; Error on port WB_CPUDataIn: Expected value is %b, Actual value is %b",WB_CPUDataIn,WB_CPUDataIn_actual); end end //Always block for monitoring port "MEM_CPUDataOut"; always @(MEM_CPUDataOut or MEM_CPUDataOut_actual) begin #MEM_CPUDataOut_WaitTime if (compare_MEM_CPUDataOut(MEM_CPUDataOut,MEM_CPUDataOut_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port MEM_CPUDataOut: Expected value is %b, Actual value is %b",MEM_CPUDataOut,MEM_CPUDataOut_actual); $display($realtime,,"ps; Error on port MEM_CPUDataOut: Expected value is %b, Actual value is %b",MEM_CPUDataOut,MEM_CPUDataOut_actual); end end //Always block for monitoring port "MEM_ALUOut"; always @(MEM_ALUOut or MEM_ALUOut_actual) begin #MEM_ALUOut_WaitTime if (compare_MEM_ALUOut(MEM_ALUOut,MEM_ALUOut_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port MEM_ALUOut: Expected value is %b, Actual value is %b",MEM_ALUOut,MEM_ALUOut_actual); $display($realtime,,"ps; Error on port MEM_ALUOut: Expected value is %b, Actual value is %b",MEM_ALUOut,MEM_ALUOut_actual); end end //Always block for monitoring port "WB_ALUOut"; always @(WB_ALUOut or WB_ALUOut_actual) begin #WB_ALUOut_WaitTime if (compare_WB_ALUOut(WB_ALUOut,WB_ALUOut_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port WB_ALUOut: Expected value is %b, Actual value is %b",WB_ALUOut,WB_ALUOut_actual); $display($realtime,,"ps; Error on port WB_ALUOut: Expected value is %b, Actual value is %b",WB_ALUOut,WB_ALUOut_actual); end end //Always block for monitoring port "Reg1"; always @(Reg1 or Reg1_actual) begin #Reg1_WaitTime if (compare_Reg1(Reg1,Reg1_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg1: Expected value is %b, Actual value is %b",Reg1,Reg1_actual); $display($realtime,,"ps; Error on port Reg1: Expected value is %b, Actual value is %b",Reg1,Reg1_actual); end end //Always block for monitoring port "Reg2"; always @(Reg2 or Reg2_actual) begin #Reg2_WaitTime if (compare_Reg2(Reg2,Reg2_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg2: Expected value is %b, Actual value is %b",Reg2,Reg2_actual); $display($realtime,,"ps; Error on port Reg2: Expected value is %b, Actual value is %b",Reg2,Reg2_actual); end end //Always block for monitoring port "Reg3"; always @(Reg3 or Reg3_actual) begin #Reg3_WaitTime if (compare_Reg3(Reg3,Reg3_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg3: Expected value is %b, Actual value is %b",Reg3,Reg3_actual); $display($realtime,,"ps; Error on port Reg3: Expected value is %b, Actual value is %b",Reg3,Reg3_actual); end end //Always block for monitoring port "Reg4"; always @(Reg4 or Reg4_actual) begin #Reg4_WaitTime if (compare_Reg4(Reg4,Reg4_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg4: Expected value is %b, Actual value is %b",Reg4,Reg4_actual); $display($realtime,,"ps; Error on port Reg4: Expected value is %b, Actual value is %b",Reg4,Reg4_actual); end end //Always block for monitoring port "Reg5"; always @(Reg5 or Reg5_actual) begin #Reg5_WaitTime if (compare_Reg5(Reg5,Reg5_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg5: Expected value is %b, Actual value is %b",Reg5,Reg5_actual); $display($realtime,,"ps; Error on port Reg5: Expected value is %b, Actual value is %b",Reg5,Reg5_actual); end end //Always block for monitoring port "Reg6"; always @(Reg6 or Reg6_actual) begin #Reg6_WaitTime if (compare_Reg6(Reg6,Reg6_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg6: Expected value is %b, Actual value is %b",Reg6,Reg6_actual); $display($realtime,,"ps; Error on port Reg6: Expected value is %b, Actual value is %b",Reg6,Reg6_actual); end end //Always block for monitoring port "Reg7"; always @(Reg7 or Reg7_actual) begin #Reg7_WaitTime if (compare_Reg7(Reg7,Reg7_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg7: Expected value is %b, Actual value is %b",Reg7,Reg7_actual); $display($realtime,,"ps; Error on port Reg7: Expected value is %b, Actual value is %b",Reg7,Reg7_actual); end end //Always block for monitoring port "Reg8"; always @(Reg8 or Reg8_actual) begin #Reg8_WaitTime if (compare_Reg8(Reg8,Reg8_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg8: Expected value is %b, Actual value is %b",Reg8,Reg8_actual); $display($realtime,,"ps; Error on port Reg8: Expected value is %b, Actual value is %b",Reg8,Reg8_actual); end end //Always block for monitoring port "Reg9"; always @(Reg9 or Reg9_actual) begin #Reg9_WaitTime if (compare_Reg9(Reg9,Reg9_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg9: Expected value is %b, Actual value is %b",Reg9,Reg9_actual); $display($realtime,,"ps; Error on port Reg9: Expected value is %b, Actual value is %b",Reg9,Reg9_actual); end end //Always block for monitoring port "Reg10"; always @(Reg10 or Reg10_actual) begin #Reg10_WaitTime if (compare_Reg10(Reg10,Reg10_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg10: Expected value is %b, Actual value is %b",Reg10,Reg10_actual); $display($realtime,,"ps; Error on port Reg10: Expected value is %b, Actual value is %b",Reg10,Reg10_actual); end end //Always block for monitoring port "Reg11"; always @(Reg11 or Reg11_actual) begin #Reg11_WaitTime if (compare_Reg11(Reg11,Reg11_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg11: Expected value is %b, Actual value is %b",Reg11,Reg11_actual); $display($realtime,,"ps; Error on port Reg11: Expected value is %b, Actual value is %b",Reg11,Reg11_actual); end end //Always block for monitoring port "Reg12"; always @(Reg12 or Reg12_actual) begin #Reg12_WaitTime if (compare_Reg12(Reg12,Reg12_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg12: Expected value is %b, Actual value is %b",Reg12,Reg12_actual); $display($realtime,,"ps; Error on port Reg12: Expected value is %b, Actual value is %b",Reg12,Reg12_actual); end end //Always block for monitoring port "Reg13"; always @(Reg13 or Reg13_actual) begin #Reg13_WaitTime if (compare_Reg13(Reg13,Reg13_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg13: Expected value is %b, Actual value is %b",Reg13,Reg13_actual); $display($realtime,,"ps; Error on port Reg13: Expected value is %b, Actual value is %b",Reg13,Reg13_actual); end end //Always block for monitoring port "Reg14"; always @(Reg14 or Reg14_actual) begin #Reg14_WaitTime if (compare_Reg14(Reg14,Reg14_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg14: Expected value is %b, Actual value is %b",Reg14,Reg14_actual); $display($realtime,,"ps; Error on port Reg14: Expected value is %b, Actual value is %b",Reg14,Reg14_actual); end end //Always block for monitoring port "Reg15"; always @(Reg15 or Reg15_actual) begin #Reg15_WaitTime if (compare_Reg15(Reg15,Reg15_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg15: Expected value is %b, Actual value is %b",Reg15,Reg15_actual); $display($realtime,,"ps; Error on port Reg15: Expected value is %b, Actual value is %b",Reg15,Reg15_actual); end end //Always block for monitoring port "Reg16"; always @(Reg16 or Reg16_actual) begin #Reg16_WaitTime if (compare_Reg16(Reg16,Reg16_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg16: Expected value is %b, Actual value is %b",Reg16,Reg16_actual); $display($realtime,,"ps; Error on port Reg16: Expected value is %b, Actual value is %b",Reg16,Reg16_actual); end end //Always block for monitoring port "Reg17"; always @(Reg17 or Reg17_actual) begin #Reg17_WaitTime if (compare_Reg17(Reg17,Reg17_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg17: Expected value is %b, Actual value is %b",Reg17,Reg17_actual); $display($realtime,,"ps; Error on port Reg17: Expected value is %b, Actual value is %b",Reg17,Reg17_actual); end end //Always block for monitoring port "Reg18"; always @(Reg18 or Reg18_actual) begin #Reg18_WaitTime if (compare_Reg18(Reg18,Reg18_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg18: Expected value is %b, Actual value is %b",Reg18,Reg18_actual); $display($realtime,,"ps; Error on port Reg18: Expected value is %b, Actual value is %b",Reg18,Reg18_actual); end end //Always block for monitoring port "Reg19"; always @(Reg19 or Reg19_actual) begin #Reg19_WaitTime if (compare_Reg19(Reg19,Reg19_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg19: Expected value is %b, Actual value is %b",Reg19,Reg19_actual); $display($realtime,,"ps; Error on port Reg19: Expected value is %b, Actual value is %b",Reg19,Reg19_actual); end end //Always block for monitoring port "Reg20"; always @(Reg20 or Reg20_actual) begin #Reg20_WaitTime if (compare_Reg20(Reg20,Reg20_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg20: Expected value is %b, Actual value is %b",Reg20,Reg20_actual); $display($realtime,,"ps; Error on port Reg20: Expected value is %b, Actual value is %b",Reg20,Reg20_actual); end end //Always block for monitoring port "Reg21"; always @(Reg21 or Reg21_actual) begin #Reg21_WaitTime if (compare_Reg21(Reg21,Reg21_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg21: Expected value is %b, Actual value is %b",Reg21,Reg21_actual); $display($realtime,,"ps; Error on port Reg21: Expected value is %b, Actual value is %b",Reg21,Reg21_actual); end end //Always block for monitoring port "Reg22"; always @(Reg22 or Reg22_actual) begin #Reg22_WaitTime if (compare_Reg22(Reg22,Reg22_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg22: Expected value is %b, Actual value is %b",Reg22,Reg22_actual); $display($realtime,,"ps; Error on port Reg22: Expected value is %b, Actual value is %b",Reg22,Reg22_actual); end end //Always block for monitoring port "Reg23"; always @(Reg23 or Reg23_actual) begin #Reg23_WaitTime if (compare_Reg23(Reg23,Reg23_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg23: Expected value is %b, Actual value is %b",Reg23,Reg23_actual); $display($realtime,,"ps; Error on port Reg23: Expected value is %b, Actual value is %b",Reg23,Reg23_actual); end end //Always block for monitoring port "Reg24"; always @(Reg24 or Reg24_actual) begin #Reg24_WaitTime if (compare_Reg24(Reg24,Reg24_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg24: Expected value is %b, Actual value is %b",Reg24,Reg24_actual); $display($realtime,,"ps; Error on port Reg24: Expected value is %b, Actual value is %b",Reg24,Reg24_actual); end end //Always block for monitoring port "Reg25"; always @(Reg25 or Reg25_actual) begin #Reg25_WaitTime if (compare_Reg25(Reg25,Reg25_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg25: Expected value is %b, Actual value is %b",Reg25,Reg25_actual); $display($realtime,,"ps; Error on port Reg25: Expected value is %b, Actual value is %b",Reg25,Reg25_actual); end end //Always block for monitoring port "Reg26"; always @(Reg26 or Reg26_actual) begin #Reg26_WaitTime if (compare_Reg26(Reg26,Reg26_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg26: Expected value is %b, Actual value is %b",Reg26,Reg26_actual); $display($realtime,,"ps; Error on port Reg26: Expected value is %b, Actual value is %b",Reg26,Reg26_actual); end end //Always block for monitoring port "Reg27"; always @(Reg27 or Reg27_actual) begin #Reg27_WaitTime if (compare_Reg27(Reg27,Reg27_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg27: Expected value is %b, Actual value is %b",Reg27,Reg27_actual); $display($realtime,,"ps; Error on port Reg27: Expected value is %b, Actual value is %b",Reg27,Reg27_actual); end end //Always block for monitoring port "Reg28"; always @(Reg28 or Reg28_actual) begin #Reg28_WaitTime if (compare_Reg28(Reg28,Reg28_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg28: Expected value is %b, Actual value is %b",Reg28,Reg28_actual); $display($realtime,,"ps; Error on port Reg28: Expected value is %b, Actual value is %b",Reg28,Reg28_actual); end end //Always block for monitoring port "Reg29"; always @(Reg29 or Reg29_actual) begin #Reg29_WaitTime if (compare_Reg29(Reg29,Reg29_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg29: Expected value is %b, Actual value is %b",Reg29,Reg29_actual); $display($realtime,,"ps; Error on port Reg29: Expected value is %b, Actual value is %b",Reg29,Reg29_actual); end end //Always block for monitoring port "Reg30"; always @(Reg30 or Reg30_actual) begin #Reg30_WaitTime if (compare_Reg30(Reg30,Reg30_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg30: Expected value is %b, Actual value is %b",Reg30,Reg30_actual); $display($realtime,,"ps; Error on port Reg30: Expected value is %b, Actual value is %b",Reg30,Reg30_actual); end end //Always block for monitoring port "Reg31"; always @(Reg31 or Reg31_actual) begin #Reg31_WaitTime if (compare_Reg31(Reg31,Reg31_actual)) begin errors_counter = errors_counter + 1; $fdisplay(report_file,$realtime,,"ps; Port Reg31: Expected value is %b, Actual value is %b",Reg31,Reg31_actual); $display($realtime,,"ps; Error on port Reg31: Expected value is %b, Actual value is %b",Reg31,Reg31_actual); end end endmodule