//-----------------------------------------------------------------------------
//
// Title       : cpu_wrapper
// Design      : lab3
// Author      : Steven
// Company     : University of Washington CSE
//
//-----------------------------------------------------------------------------
//
// File        : cpu_wrapper.v
// Generated   : Sun Oct 29 22:40:11 2006
// From        : interface description file
// By          : Itf2Vhdl ver. 1.21
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {cpu_wrapper}}
module cpu_wrapper ( 
	output wire [31:0] Reg1 , Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15, Reg16, Reg17, Reg18, Reg19, Reg20, Reg21, Reg22, Reg23, Reg24, Reg25, Reg26, Reg27, Reg28, Reg29, Reg30, Reg31,
	output wire [31:0] ID_Inst,EX_Inst,MEM_Inst,WB_Inst,
	output wire [4:0] EX_WriteReg, MEM_WriteReg, WB_WriteReg,
	output wire [31:0] MEM_ALUOut, MEM_CPUDataOut, WB_ALUOut, WB_CPUDataIn,
	input wire CLK ,
	input wire RESET ,
	input wire [31:0] CPUDataIn ,Inst,
	output wire [31:0] CPUDataOut ,ALUOut, PCOut,
	output wire [31:0] IF_NextPC, ID_NextPC, EX_NextPC,
	output wire Store , SignedLoad, EX_RegWrite, MEM_RegWrite, WB_RegWrite,
	output wire [1:0] MemSize 
	);

cpu CPU (.CLK(CLK),
	.RESET(RESET),
	.CPUDataIn(CPUDataIn),
	.Inst(Inst),
	.SignedLoad(SignedLoad),
	.Store(Store),
	.ALUOut(ALUOut),
	.CPUDataOut(CPUDataOut),
	.MemSize(MemSize),
	.PCOut(PCOut)
);

assign Reg1 = CPU.Regfile.RF[1];
assign Reg2 = CPU.Regfile.RF[2];
assign Reg3 = CPU.Regfile.RF[3];
assign Reg4 = CPU.Regfile.RF[4];
assign Reg5 = CPU.Regfile.RF[5];
assign Reg6 = CPU.Regfile.RF[6];
assign Reg7 = CPU.Regfile.RF[7];
assign Reg8 = CPU.Regfile.RF[8];
assign Reg9 = CPU.Regfile.RF[9];
assign Reg10 = CPU.Regfile.RF[10];
assign Reg11 = CPU.Regfile.RF[11];
assign Reg12 = CPU.Regfile.RF[12];
assign Reg13 = CPU.Regfile.RF[13];
assign Reg14 = CPU.Regfile.RF[14];
assign Reg15 = CPU.Regfile.RF[15];
assign Reg16 = CPU.Regfile.RF[16];
assign Reg17 = CPU.Regfile.RF[17];
assign Reg18 = CPU.Regfile.RF[18];
assign Reg19 = CPU.Regfile.RF[19];
assign Reg20 = CPU.Regfile.RF[20];
assign Reg21 = CPU.Regfile.RF[21];
assign Reg22 = CPU.Regfile.RF[22];
assign Reg23 = CPU.Regfile.RF[23];
assign Reg24 = CPU.Regfile.RF[24];
assign Reg25 = CPU.Regfile.RF[25];
assign Reg26 = CPU.Regfile.RF[26];
assign Reg27 = CPU.Regfile.RF[27];
assign Reg28 = CPU.Regfile.RF[28];
assign Reg29 = CPU.Regfile.RF[29];
assign Reg30 = CPU.Regfile.RF[30];
assign Reg31 = CPU.Regfile.RF[31];

assign ID_Inst = CPU.IFIDReg.ID_Inst;
assign EX_Inst = CPU.IDEXReg.EX_Inst;
assign MEM_Inst = CPU.EXMEMReg.MEM_Inst;
assign WB_Inst = CPU.MEMWBReg.WB_Inst;
assign EX_WriteReg = CPU.IDEXReg.EX_WriteReg;
assign MEM_WriteReg = CPU.EXMEMReg.MEM_WriteReg;
assign WB_WriteReg = CPU.MEMWBReg.WB_WriteReg;
assign MEM_ALUOut = CPU.EXMEMReg.MEM_ALUOut;
assign MEM_CPUDataOut = CPU.EXMEMReg.MEM_CPUDataOut;
assign WB_ALUOut = CPU.MEMWBReg.WB_ALUOut;
assign WB_CPUDataIn = CPU.MEMWBReg.WB_CPUDataIn;	
assign EX_RegWrite = CPU.IDEXReg.EX_RegWrite;
assign MEM_RegWrite = CPU.EXMEMReg.MEM_RegWrite;
assign WB_RegWrite = CPU.MEMWBReg.WB_RegWrite;
assign IF_NextPC = CPU.IFIDReg.IF_NextPC;
assign ID_NextPC = CPU.IFIDReg.ID_NextPC;
assign EX_NextPC = CPU.IDEXReg.EX_NextPC;
endmodule