//-----------------------------------------------------------------------------
//
// Title       : phase2_tf
// Design      : lab2
// Author      : Steven
// Company     : University of Washington CSE
//
//-----------------------------------------------------------------------------
//
// File        : phase2_tf.v
// Generated   : Wed Sep 20 15:57:57 2006
// From        : 
// By          : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------

`timescale 1ps / 1ps
module phase2_tf;


//Internal signals declarations:
wire [1:0]AluOp_actual;
reg [1:0]AluOp;
wire SrcASel_actual;
reg SrcASel;
wire SrcBSel_actual;
reg SrcBSel;
wire [1:0]ExtOp_actual;
reg [1:0]ExtOp;
wire JAL_actual;
reg JAL;
wire JR_actual;
reg JR;
wire Branch_actual;
reg Branch;
wire Jump_actual;
reg Jump;
wire RegWrite_actual;
reg RegWrite;
wire WriteToRD_actual;
reg WriteToRD;
wire Load_actual;
reg Load;
wire Store_actual;
reg Store;
wire SignedLoad_actual;
reg SignedLoad;
wire [1:0]MemSize_actual;
reg [1:0]MemSize;
reg [5:0]Op;
reg [5:0]func;
//LOG file declaration.
integer report_file;

//Wait time declaration used in ports monitoring.
//One parameter is declared for every port.
parameter Default_wait_time = 10;
parameter AluOp_WaitTime = Default_wait_time;//WaitTime Parameter for port AluOp
parameter SrcASel_WaitTime = Default_wait_time;//WaitTime Parameter for port SrcASel
parameter SrcBSel_WaitTime = Default_wait_time;//WaitTime Parameter for port SrcBSel
parameter ExtOp_WaitTime = Default_wait_time;//WaitTime Parameter for port ExtOp
parameter JAL_WaitTime = Default_wait_time;//WaitTime Parameter for port JAL
parameter JR_WaitTime = Default_wait_time;//WaitTime Parameter for port JR
parameter Branch_WaitTime = Default_wait_time;//WaitTime Parameter for port Branch
parameter Jump_WaitTime = Default_wait_time;//WaitTime Parameter for port Jump
parameter RegWrite_WaitTime = Default_wait_time;//WaitTime Parameter for port RegWrite
parameter WriteToRD_WaitTime = Default_wait_time;//WaitTime Parameter for port WriteToRD
parameter Load_WaitTime = Default_wait_time;//WaitTime Parameter for port Load
parameter Store_WaitTime = Default_wait_time;//WaitTime Parameter for port Store
parameter SignedLoad_WaitTime = Default_wait_time;//WaitTime Parameter for port SignedLoad
parameter MemSize_WaitTime = Default_wait_time;//WaitTime Parameter for port MemSize

//Simulation time
parameter SimulationTime = 64'd2190000 + Default_wait_time + 1;

//Errors counter
integer errors_counter;

//Block of Comparison functions declarations. A separate function for each output port is defined.
//Comparison function for port "AluOp"
function compare_AluOp;
input [1:0] UUT_output;
input [1:0] PATTERN;
	begin
		if (UUT_output != PATTERN) compare_AluOp = 1'b1;
		else compare_AluOp = 1'b0;
	end
endfunction
//Comparison function for port "SrcASel"
function compare_SrcASel;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output != PATTERN) compare_SrcASel = 1'b1;
		else compare_SrcASel = 1'b0;
	end
endfunction
//Comparison function for port "SrcBSel"
function compare_SrcBSel;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output != PATTERN) compare_SrcBSel = 1'b1;
		else compare_SrcBSel = 1'b0;
	end
endfunction
//Comparison function for port "ExtOp"
function compare_ExtOp;
input [1:0] UUT_output;
input [1:0] PATTERN;
	begin
		if (UUT_output != PATTERN) compare_ExtOp = 1'b1;
		else compare_ExtOp = 1'b0;
	end
endfunction
//Comparison function for port "JAL"
function compare_JAL;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_JAL = 1'b1;
		else compare_JAL = 1'b0;
	end
endfunction
//Comparison function for port "JR"
function compare_JR;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_JR = 1'b1;
		else compare_JR = 1'b0;
	end
endfunction
//Comparison function for port "Branch"
function compare_Branch;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Branch = 1'b1;
		else compare_Branch = 1'b0;
	end
endfunction
//Comparison function for port "Jump"
function compare_Jump;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Jump = 1'b1;
		else compare_Jump = 1'b0;
	end
endfunction
//Comparison function for port "RegWrite"
function compare_RegWrite;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_RegWrite = 1'b1;
		else compare_RegWrite = 1'b0;
	end
endfunction
//Comparison function for port "WriteToRD"
function compare_WriteToRD;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output != PATTERN) compare_WriteToRD = 1'b1;
		else compare_WriteToRD = 1'b0;
	end
endfunction
//Comparison function for port "Load"
function compare_Load;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output != PATTERN) compare_Load = 1'b1;
		else compare_Load = 1'b0;
	end
endfunction
//Comparison function for port "Store"
function compare_Store;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Store = 1'b1;
		else compare_Store = 1'b0;
	end
endfunction
//Comparison function for port "SignedLoad"
function compare_SignedLoad;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output != PATTERN) compare_SignedLoad = 1'b1;
		else compare_SignedLoad = 1'b0;
	end
endfunction
//Comparison function for port "MemSize"
function compare_MemSize;
input [1:0] UUT_output;
input [1:0] PATTERN;
	begin
		if (UUT_output != PATTERN) compare_MemSize = 1'b1;
		else compare_MemSize = 1'b0;
	end
endfunction

// Unit Under Test port map
	Controller UUT (
		.AluOp(AluOp_actual),
		.SrcASel(SrcASel_actual),
		.SrcBSel(SrcBSel_actual),
		.ExtOp(ExtOp_actual),
		.JAL(JAL_actual),
		.JR(JR_actual),
		.Branch(Branch_actual),
		.Jump(Jump_actual),
		.RegWrite(RegWrite_actual),
		.WriteToRD(WriteToRD_actual),
		.Load(Load_actual),
		.Store(Store_actual),
		.SignedLoad(SignedLoad_actual),
		.MemSize(MemSize_actual),
		.Op(Op),
		.func(func));

initial
	begin
		report_file=$fopen("$DSN\\src\\Tests\\phase2_report.log");
		errors_counter = 0;
		#SimulationTime;
		if (errors_counter)
		begin
			$display("Errors were encountered, differences are listed in phase2_report.log");
			$fdisplay(report_file,"Some vectors failed.");
		end
		else
		begin
			$display("All vectors passed.");
			$fdisplay(report_file,"All vectors passed.");
		end
		$fclose(report_file);
		$finish;
	end

//Below code was generated based on waveform file: "e:\my_designs\AndrewH\lab2\compile\phase2.vhr"

initial
begin : STIMUL // begin of stimulus process
	#0
	SrcASel = 1'b1;
	AluOp = 2'b10;
	ExtOp = 2'b11;
	SrcBSel = 1'b0;
	WriteToRD = 1'b1;
	Jump = 1'b0;
	Load = 1'b0;
	Branch = 1'b0;
	JAL = 1'b0;
	JR = 1'b0;
	RegWrite = 1'b1;
	SignedLoad = 1'b0;
	Store = 1'b0;
	Op = 6'b000000;
	MemSize = 2'b??;
	func = 6'b000000;
    #350000; //0
	func = 6'b000010;
    #40000; //350000
	func = 6'b000011;
    #40000; //390000
	SrcASel = 1'b0;
	ExtOp = 2'b00;
	func = 6'b000100;
    #40000; //430000
	func = 6'b000110;
    #40000; //470000
	func = 6'b000111;
    #40000; //510000
	AluOp = 2'b00;
	Jump = 1'b1;
	JAL = 1'b1;
	JR = 1'b1;
        ExtOp = 2'b??;    // don't care for JALR/JR
        SignedLoad = 1'b?; // don't care
	func = 6'b001001;
    #40000; //550000
	WriteToRD = 1'b?; // don't care for JR
        AluOp = 2'b??;    // don't care for JR
	SrcASel = 1'b?;
	SrcBSel = 1'b?;
	JAL = 1'b0;
	RegWrite = 1'b0;
	Load = 1'b?;      // we aren't writing, so who cares?
	func = 6'b001000;
    #40000; //590000
	AluOp = 2'b10;
	WriteToRD = 1'b1;
	Jump = 1'b0;
	JR = 1'b0;
	RegWrite = 1'b1;
	Load = 1'b0; // use ALUOut
	func = 6'b010000;
    #40000; //630000
        SrcASel = 1'b0; // need the RS value
	WriteToRD = 1'b?;
	RegWrite = 1'b0;
	Load = 1'b?; // load doesn't matter
	func = 6'b010001;
    #40000; //670000
    	SrcASel = 1'b?; // don't care about ALU inputs
    	WriteToRD = 1'b1;
	RegWrite = 1'b1;
	Load = 1'b0;
	func = 6'b010010;
    #40000; //710000
    	SrcASel = 1'b0; // need RS
	Load = 1'b?;    // don't need it
	WriteToRD = 1'b?; // don't need it
	RegWrite = 1'b0;
	func = 6'b010011;
    #40000; //750000
    	SrcBSel = 1'b0; // need RT
	func = 6'b011000;
    #40000; //790000
	func = 6'b011001;
    #40000; //830000
	RegWrite = 1'b1;
	WriteToRD = 1'b1;
	Load = 1'b0;
	func = 6'b100000;
    #40000; //870000
	func = 6'b100001;
    #40000; //910000
	func = 6'b100010;
    #40000; //950000
	func = 6'b100011;
    #40000; //990000
	func = 6'b100100;
    #40000; //1030000
	func = 6'b100101;
    #40000; //1070000
	func = 6'b100110;
    #40000; //1110000
	func = 6'b100111;
    #40000; //1150000
	func = 6'b101010;
    #40000; //1190000
	func = 6'b101011;
    #40000; //1230000
	AluOp = 2'b??;
	SrcASel = 1'b?;
	SrcBSel = 1'b?;
	Load = 1'b?;
	WriteToRD = 1'b?;
	Jump = 1'b1;
	RegWrite = 1'b0;
	Op = 6'b000010;
	func = 6'b101110;
    #40000; //1270000
	JAL = 1'b1;
	RegWrite = 1'b1;
	AluOp = 2'b00;
	SrcASel = 1'b0;
	SrcBSel = 1'b0;
	Load = 1'b0;
	WriteToRD = 1'b0;
	Op = 6'b000011;
    #40000; //1310000
	AluOp = 2'b01;
	Jump = 1'b0;
	Branch = 1'b1;
	JAL = 1'b0;
	RegWrite = 1'b0;
	WriteToRD = 1'b?;
	Load = 1'b?;
	Op = 6'b000100;
	func = 6'b010011;
    #40000; //1350000
	Op = 6'b000101;
	func = 6'b010010;
    #40000; //1390000
	AluOp = 2'b00;
	Op = 6'b000110;
	func = 6'b010001;
    #40000; //1430000
	Op = 6'b000111;
	func = 6'b010000;
    #40000; //1470000
	AluOp = 2'b11;
	ExtOp = 2'b01;
	SrcBSel = 1'b1;
	Branch = 1'b0;
	RegWrite = 1'b1;
	WriteToRD = 1'b0;
	Load = 1'b0;
	Op = 6'b001000;
	func = 6'b000101;
    #40000; //1510000
	Op = 6'b001001;
	func = 6'b111011;
    #40000; //1550000
	Op = 6'b001010;
	func = 6'b111111;
    #40000; //1590000
	Op = 6'b001011;
    #40000; //1630000
	ExtOp = 2'b00;
	Op = 6'b001100;
	func = 6'b001011;
    #40000; //1670000
	Op = 6'b001101;
    #40000; //1710000
	Op = 6'b001110;
	func = 6'b000110;
    #40000; //1750000
	ExtOp = 2'b10;
	Op = 6'b001111;
	func = 6'b011100;
    #40000; //1790000
	AluOp = 2'b00;
	ExtOp = 2'b01;
	Load = 1'b1;
	SignedLoad = 1'b1;
	Op = 6'b100000;
	MemSize = 2'b01;
	func = 6'b000000;
    #40000; //1830000
	Op = 6'b100001;
	MemSize = 2'b10;
	func = 6'b000010;
    #40000; //1870000
	SignedLoad = 1'b0;
	Op = 6'b100011;
	MemSize = 2'b11;
	func = 6'b000000;
    #40000; //1910000
	Load = 1'b1;
	RegWrite = 1'b1;
	Op = 6'b100100;
	MemSize = 2'b01;
    #40000; //1950000
	Op = 6'b100101;
	MemSize = 2'b10;
	func = 6'b000010;
    #40000; //1990000
	Load = 1'b?;
	SignedLoad = 1'b?;
	RegWrite = 1'b0;
	Store = 1'b1;
	Op = 6'b101000;
	MemSize = 2'b01;
	func = 6'b000011;
    #40000; //2030000
	Op = 6'b101001;
	MemSize = 2'b10;
	func = 6'b000010;
    #40000; //2070000
	Op = 6'b101011;
	MemSize = 2'b11;
	func = 6'b000000;
    #40000; //2110000
	SrcASel = 1'b1;
	AluOp = 2'b10;
	ExtOp = 2'b11;
	SrcBSel = 1'b0;
	WriteToRD = 1'b1;
	RegWrite = 1'b1;
	Store = 1'b0;
	Op = 6'b000000;
	MemSize = 2'b00;
    #40000; //2150000
	SrcASel = 1'bx;
	AluOp = 2'bXX;
	ExtOp = 2'bXX;
	SrcBSel = 1'bx;
	WriteToRD = 1'bx;
	Jump = 1'bx;
	Load = 1'bx;
	Branch = 1'bx;
	JAL = 1'bx;
	JR = 1'bx;
	RegWrite = 1'bx;
	SignedLoad = 1'bx;
	Store = 1'bx;
	Op = 6'bXXXXXX;
	MemSize = 2'bXX;
	func = 6'bXXXXXX;
end // end of stimulus process




//Set of always bloks for ports monitoring.
//One block per output port.
//Always block for monitoring port "AluOp";
always @(AluOp or AluOp_actual)
	begin
		#AluOp_WaitTime
		if (compare_AluOp(AluOp,AluOp_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port AluOp: Expected value is %b, Actual value is %b",AluOp,AluOp_actual);
			$display($realtime,,"ps; Error on port AluOp: Expected value is %b, Actual value is %b",AluOp,AluOp_actual);
		end
	end
//Always block for monitoring port "SrcASel";
always @(SrcASel or SrcASel_actual)
	begin
		#SrcASel_WaitTime
		if (compare_SrcASel(SrcASel,SrcASel_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port SrcASel: Expected value is %b, Actual value is %b",SrcASel,SrcASel_actual);
			$display($realtime,,"ps; Error on port SrcASel: Expected value is %b, Actual value is %b",SrcASel,SrcASel_actual);
		end
	end
//Always block for monitoring port "SrcBSel";
always @(SrcBSel or SrcBSel_actual)
	begin
		#SrcBSel_WaitTime
		if (compare_SrcBSel(SrcBSel,SrcBSel_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port SrcBSel: Expected value is %b, Actual value is %b",SrcBSel,SrcBSel_actual);
			$display($realtime,,"ps; Error on port SrcBSel: Expected value is %b, Actual value is %b",SrcBSel,SrcBSel_actual);
		end
	end
//Always block for monitoring port "ExtOp";
always @(ExtOp or ExtOp_actual)
	begin
		#ExtOp_WaitTime
		if (compare_ExtOp(ExtOp,ExtOp_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port ExtOp: Expected value is %b, Actual value is %b",ExtOp,ExtOp_actual);
			$display($realtime,,"ps; Error on port ExtOp: Expected value is %b, Actual value is %b",ExtOp,ExtOp_actual);
		end
	end
//Always block for monitoring port "JAL";
always @(JAL or JAL_actual)
	begin
		#JAL_WaitTime
		if (compare_JAL(JAL,JAL_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port JAL: Expected value is %b, Actual value is %b",JAL,JAL_actual);
			$display($realtime,,"ps; Error on port JAL: Expected value is %b, Actual value is %b",JAL,JAL_actual);
		end
	end
//Always block for monitoring port "JR";
always @(JR or JR_actual)
	begin
		#JR_WaitTime
		if (compare_JR(JR,JR_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port JR: Expected value is %b, Actual value is %b",JR,JR_actual);
			$display($realtime,,"ps; Error on port JR: Expected value is %b, Actual value is %b",JR,JR_actual);
		end
	end
//Always block for monitoring port "Branch";
always @(Branch or Branch_actual)
	begin
		#Branch_WaitTime
		if (compare_Branch(Branch,Branch_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Branch: Expected value is %b, Actual value is %b",Branch,Branch_actual);
			$display($realtime,,"ps; Error on port Branch: Expected value is %b, Actual value is %b",Branch,Branch_actual);
		end
	end
//Always block for monitoring port "Jump";
always @(Jump or Jump_actual)
	begin
		#Jump_WaitTime
		if (compare_Jump(Jump,Jump_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Jump: Expected value is %b, Actual value is %b",Jump,Jump_actual);
			$display($realtime,,"ps; Error on port Jump: Expected value is %b, Actual value is %b",Jump,Jump_actual);
		end
	end
//Always block for monitoring port "RegWrite";
always @(RegWrite or RegWrite_actual)
	begin
		#RegWrite_WaitTime
		if (compare_RegWrite(RegWrite,RegWrite_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port RegWrite: Expected value is %b, Actual value is %b",RegWrite,RegWrite_actual);
			$display($realtime,,"ps; Error on port RegWrite: Expected value is %b, Actual value is %b",RegWrite,RegWrite_actual);
		end
	end
//Always block for monitoring port "WriteToRD";
always @(WriteToRD or WriteToRD_actual)
	begin
		#WriteToRD_WaitTime
		if (compare_WriteToRD(WriteToRD,WriteToRD_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port WriteToRD: Expected value is %b, Actual value is %b",WriteToRD,WriteToRD_actual);
			$display($realtime,,"ps; Error on port WriteToRD: Expected value is %b, Actual value is %b",WriteToRD,WriteToRD_actual);
		end
	end
//Always block for monitoring port "Load";
always @(Load or Load_actual)
	begin
		#Load_WaitTime
		if (compare_Load(Load,Load_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Load: Expected value is %b, Actual value is %b",Load,Load_actual);
			$display($realtime,,"ps; Error on port Load: Expected value is %b, Actual value is %b",Load,Load_actual);
		end
	end
//Always block for monitoring port "Store";
always @(Store or Store_actual)
	begin
		#Store_WaitTime
		if (compare_Store(Store,Store_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Store: Expected value is %b, Actual value is %b",Store,Store_actual);
			$display($realtime,,"ps; Error on port Store: Expected value is %b, Actual value is %b",Store,Store_actual);
		end
	end
//Always block for monitoring port "SignedLoad";
always @(SignedLoad or SignedLoad_actual)
	begin
		#SignedLoad_WaitTime
		if (compare_SignedLoad(SignedLoad,SignedLoad_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port SignedLoad: Expected value is %b, Actual value is %b",SignedLoad,SignedLoad_actual);
			$display($realtime,,"ps; Error on port SignedLoad: Expected value is %b, Actual value is %b",SignedLoad,SignedLoad_actual);
		end
	end
//Always block for monitoring port "MemSize";
always @(MemSize or MemSize_actual)
	begin
		#MemSize_WaitTime
		if (compare_MemSize(MemSize,MemSize_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port MemSize: Expected value is %b, Actual value is %b",MemSize,MemSize_actual);
			$display($realtime,,"ps; Error on port MemSize: Expected value is %b, Actual value is %b",MemSize,MemSize_actual);
		end
	end

endmodule