//-----------------------------------------------------------------------------
//
// Title       : phase1_tf
// Design      : lab2
// Author      : Steven
// Company     : University of Washington CSE
//
//-----------------------------------------------------------------------------
//
// File        : phase1_tf.v
// Generated   : Wed Sep 20 14:16:43 2006
// From        : 
// By          : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------

`timescale 1ps / 1ps
module phase1_tf;


//Internal signals declarations:
reg CLK;
reg RESET;
reg Branch;
reg SrcBSel;
reg SrcASel;
reg RegWrite;
wire Overflow_actual;
reg Overflow;
reg Load;
reg Jump;
reg JAL;
reg JR;
wire [31:0]PCOut_actual;
reg [31:0]PCOut;
reg [31:0]Inst;
reg [1:0]ExtOp;
wire [31:0]CPUDataOut_actual;
reg [31:0]CPUDataOut;
reg [31:0]CPUDataIn;
wire [31:0]ALUOut_actual;
reg [31:0]ALUOut;
reg [1:0]ALUOp;
wire Zilch_actual;
reg Zilch;
reg WriteToRD;
//LOG file declaration.
integer report_file;

//Wait time declaration used in ports monitoring.
//One parameter is declared for every port.
parameter Default_wait_time = 10;
parameter Overflow_WaitTime = Default_wait_time;//WaitTime Parameter for port Overflow
parameter PCOut_WaitTime = Default_wait_time;//WaitTime Parameter for port PCOut
parameter CPUDataOut_WaitTime = Default_wait_time;//WaitTime Parameter for port CPUDataOut
parameter ALUOut_WaitTime = Default_wait_time;//WaitTime Parameter for port ALUOut
parameter Zilch_WaitTime = Default_wait_time;//WaitTime Parameter for port Zilch

//Simulation time
parameter SimulationTime = 64'd950000 + Default_wait_time + 1;

//Errors counter
integer errors_counter;

//Block of Comparison functions declarations. A separate function for each output port is defined.
//Comparison function for port "Overflow"
function compare_Overflow;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Overflow = 1'b1;
		else compare_Overflow = 1'b0;
	end
endfunction
//Comparison function for port "PCOut"
function compare_PCOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_PCOut = 1'b1;
		else compare_PCOut = 1'b0;
	end
endfunction
//Comparison function for port "CPUDataOut"
function compare_CPUDataOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_CPUDataOut = 1'b1;
		else compare_CPUDataOut = 1'b0;
	end
endfunction
//Comparison function for port "ALUOut"
function compare_ALUOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_ALUOut = 1'b1;
		else compare_ALUOut = 1'b0;
	end
endfunction
//Comparison function for port "Zilch"
function compare_Zilch;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Zilch = 1'b1;
		else compare_Zilch = 1'b0;
	end
endfunction

// Unit Under Test port map
	Datapath UUT (
		.CLK(CLK),
		.RESET(RESET),
		.Branch(Branch),
		.SrcBSel(SrcBSel),
		.SrcASel(SrcASel),
		.RegWrite(RegWrite),
		.Overflow(Overflow_actual),
		.Load(Load),
		.Jump(Jump),
		.JAL(JAL),
		.JR(JR),
		.PCOut(PCOut_actual),
		.Inst(Inst),
		.ExtOp(ExtOp),
		.CPUDataOut(CPUDataOut_actual),
		.CPUDataIn(CPUDataIn),
		.ALUOut(ALUOut_actual),
		.ALUOp(ALUOp),
		.Zilch(Zilch_actual),
		.WriteToRD(WriteToRD));

initial
	begin
		report_file=$fopen("$DSN\\src\\Tests\\phase1_report.log");
		errors_counter = 0;
		#SimulationTime;
		if (errors_counter)
		begin
			$display("Errors were encountered, differences are listed in phase1_report.log");
			$fdisplay(report_file,"Some vectors failed.");
		end
		else
		begin
			$display("All vectors passed.");
			$fdisplay(report_file,"All vectors passed.");
		end
		$fclose(report_file);
		$finish;
	end

//Below code was generated based on waveform file: "e:\my_designs\AndrewH\lab2\compile\phase1.vhr"

initial
begin : STIMUL // begin of stimulus process
	#0
	CLK = 1'b0;
	RESET = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b0;
	Overflow = 1'b0;
	SrcBSel = 1'b1;
	Branch = 1'b0;
	PCOut = 32'b00000000000000000000000000000000;
	JR = 1'b0;
	Jump = 1'b0;
	Load = 1'b0;
	JAL = 1'b0;
	Inst = 32'b00111100000001000000000000000000;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ExtOp = 2'b10;
	CPUDataIn = 32'b000000000000000000000000XXXXXXXX;
	ALUOut = 32'b00000000000000000000000000000000;
	WriteToRD = 1'b0;
	Zilch = 1'b1;
	ALUOp = 2'b11;
    #340000; //0
	RESET = 1'b0;
    #10000; //340000
	CLK = 1'b1;
	PCOut = 32'b00000000000000000000000000000100;
	Inst = 32'b00100000100001010000000000011000;
	ExtOp = 2'b01;
	ALUOut = 32'b00000000000000000000000000011000;
	Zilch = 1'b0;
    #20000; //350000
	CLK = 1'b0;
    #20000; //370000
	CLK = 1'b1;
	RegWrite = 1'b0;
	SrcBSel = 1'b0;
	PCOut = 32'b00000000000000000000000000001000;
	JR = 1'b1;
	Jump = 1'b1;
	Inst = 32'b00000000101000000000000000001000;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ExtOp = 2'b00;
	WriteToRD = 1'b0;
	ALUOp = 2'b00;
    #20000; //390000
	CLK = 1'b0;
    #20000; //410000
	CLK = 1'b1;
	RegWrite = 1'b1;
	PCOut = 32'b00000000000000000000000000011000;
	JR = 1'b0;
	JAL = 1'b1;
	Inst = 32'b00001100000000000000000000010000;
	ALUOut = 32'b00000000000000000000000000011100;
    #20000; //430000
	CLK = 1'b0;
    #20000; //450000
	CLK = 1'b1;
	RegWrite = 1'b0;
	PCOut = 32'b00000000000000000000000001000000;
	JR = 1'b1;
	JAL = 1'b0;
	Inst = 32'b00000011111000000000000000001000;
	WriteToRD = 1'b0;
	ALUOp = 2'b00;
    #20000; //470000
	CLK = 1'b0;
    #20000; //490000
	CLK = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b1;
	PCOut = 32'b00000000000000000000000000011100;
	JR = 1'b0;
	Jump = 1'b0;
	Inst = 32'b00000000000000000000000000000000;
	ExtOp = 2'b11;
	ALUOut = 32'b00000000000000000000000000000000;
	WriteToRD = 1'b1;
	Zilch = 1'b1;
	ALUOp = 2'b10;
    #20000; //510000
	CLK = 1'b0;
    #20000; //530000
	CLK = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b0;
	SrcBSel = 1'b1;
	PCOut = 32'b00000000000000000000000000100000;
	Inst = 32'b00100000100001100000000001001000;
	ExtOp = 2'b01;
	ALUOut = 32'b00000000000000000000000001001000;
	WriteToRD = 1'b0;
	Zilch = 1'b0;
	ALUOp = 2'b11;
    #20000; //550000
	CLK = 1'b0;
    #20000; //570000
	CLK = 1'b1;
	SrcBSel = 1'b0;
	PCOut = 32'b00000000000000000000000000100100;
	JR = 1'b1;
	Jump = 1'b1;
	JAL = 1'b1;
	Inst = 32'b00000000110000001111100000001001;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ExtOp = 2'b00;
	ALUOut = 32'b00000000000000000000000000101000;
	WriteToRD = 1'b1;
	ALUOp = 2'b00;
    #20000; //590000
	CLK = 1'b0;
    #20000; //610000
	CLK = 1'b1;
	RegWrite = 1'b0;
	PCOut = 32'b00000000000000000000000001001000;
	JAL = 1'b0;
	Inst = 32'b00000011111000000000000000001000;
	WriteToRD = 1'b0;
    #20000; //630000
	CLK = 1'b0;
    #20000; //650000
	CLK = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b1;
	PCOut = 32'b00000000000000000000000000101000;
	JR = 1'b0;
	Jump = 1'b0;
	Inst = 32'b00000000000000000000000000000000;
	ExtOp = 2'b11;
	ALUOut = 32'b00000000000000000000000000000000;
	WriteToRD = 1'b1;
	Zilch = 1'b1;
	ALUOp = 2'b10;
    #20000; //670000
	CLK = 1'b0;
    #20000; //690000
	CLK = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b0;
	SrcBSel = 1'b1;
	PCOut = 32'b00000000000000000000000000101100;
	Inst = 32'b00100000100001110000000001010000;
	ExtOp = 2'b01;
	ALUOut = 32'b00000000000000000000000001010000;
	WriteToRD = 1'b0;
	Zilch = 1'b0;
	ALUOp = 2'b11;
    #20000; //710000
	CLK = 1'b0;
    #20000; //730000
	CLK = 1'b1;
	SrcBSel = 1'b0;
	PCOut = 32'b00000000000000000000000000110000;
	JR = 1'b1;
	Jump = 1'b1;
	JAL = 1'b1;
	Inst = 32'b00000000111000000100000000001001;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ExtOp = 2'b00;
	ALUOut = 32'b00000000000000000000000000110100;
	WriteToRD = 1'b1;
	ALUOp = 2'b00;
    #20000; //750000
	CLK = 1'b0;
    #20000; //770000
	CLK = 1'b1;
	RegWrite = 1'b0;
	PCOut = 32'b00000000000000000000000001010000;
	JAL = 1'b0;
	Inst = 32'b00000001000000000000000000001000;
	WriteToRD = 1'b0;
    #20000; //790000
	CLK = 1'b0;
    #20000; //810000
	CLK = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b1;
	PCOut = 32'b00000000000000000000000000110100;
	JR = 1'b0;
	Jump = 1'b0;
	Inst = 32'b00000000000000000000000000000000;
	ExtOp = 2'b11;
	ALUOut = 32'b00000000000000000000000000000000;
	WriteToRD = 1'b1;
	Zilch = 1'b1;
	ALUOp = 2'b10;
    #20000; //830000
	CLK = 1'b0;
    #20000; //850000
	CLK = 1'b1;
	RegWrite = 1'b0;
	SrcASel = 1'b0;
	PCOut = 32'b00000000000000000000000000111000;
	Jump = 1'b1;
	Inst = 32'b00001000000000000000000000011000;
	ExtOp = 2'b00;
	WriteToRD = 1'b0;
	ALUOp = 2'b00;
    #20000; //870000
	CLK = 1'b0;
    #20000; //890000
	CLK = 1'b1;
	RegWrite = 1'b1;
	SrcASel = 1'b1;
	PCOut = 32'b00000000000000000000000001100000;
	Jump = 1'b0;
	Inst = 32'b00000000000000000000000000000000;
	ExtOp = 2'b11;
	WriteToRD = 1'b1;
	ALUOp = 2'b10;
    #20000; //910000
	CLK = 1'b0;
    #20000; //930000
end // end of stimulus process
	



//Set of always bloks for ports monitoring.
//One block per output port.
//Always block for monitoring port "Overflow";
always @(Overflow or Overflow_actual)
	begin
		#Overflow_WaitTime
		if (compare_Overflow(Overflow,Overflow_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Overflow: Expected value is %b, Actual value is %b",Overflow,Overflow_actual);
			$display($realtime,,"ps; Error on port Overflow: Expected value is %b, Actual value is %b",Overflow,Overflow_actual);
		end
	end
//Always block for monitoring port "PCOut";
always @(PCOut or PCOut_actual)
	begin
		#PCOut_WaitTime
		if (compare_PCOut(PCOut,PCOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port PCOut: Expected value is %b, Actual value is %b",PCOut,PCOut_actual);
			$display($realtime,,"ps; Error on port PCOut: Expected value is %b, Actual value is %b",PCOut,PCOut_actual);
		end
	end
//Always block for monitoring port "CPUDataOut";
always @(CPUDataOut or CPUDataOut_actual)
	begin
		#CPUDataOut_WaitTime
		if (compare_CPUDataOut(CPUDataOut,CPUDataOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port CPUDataOut: Expected value is %b, Actual value is %b",CPUDataOut,CPUDataOut_actual);
			$display($realtime,,"ps; Error on port CPUDataOut: Expected value is %b, Actual value is %b",CPUDataOut,CPUDataOut_actual);
		end
	end
//Always block for monitoring port "ALUOut";
always @(ALUOut or ALUOut_actual)
	begin
		#ALUOut_WaitTime
		if (compare_ALUOut(ALUOut,ALUOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual);
			$display($realtime,,"ps; Error on port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual);
		end
	end
//Always block for monitoring port "Zilch";
always @(Zilch or Zilch_actual)
	begin
		#Zilch_WaitTime
		if (compare_Zilch(Zilch,Zilch_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Zilch: Expected value is %b, Actual value is %b",Zilch,Zilch_actual);
			$display($realtime,,"ps; Error on port Zilch: Expected value is %b, Actual value is %b",Zilch,Zilch_actual);
		end
	end

endmodule