CSE 378, Winter 2007  Machine Organization and Assembly Language Programming
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# Lab 2: Taking Control - HW

Assigned: 2/7/2007
Due: 6:00PM, 2/14/2007

### Description

The goal of the hardware portion of Lab 2 is to synthesize and implement your design, then place it on the board so that it can run a recursive program that solves the  "Towers of Hanoi" for the case of 3 discs.

Do NOT start this portion of the lab until you have verified that your design works in all the tests for the software portion.

2. Copy hanoi.spim and hanoi.s into the Assembly directory under lab2
3. Copy the Lab2_Components.{edf,ngo,ngd} into the lib378cores directory used in lab1

### Phase 1: Towers of Hanoi

The Towers of Hanoi is a simple puzzle that follows simple rules. (Towers of Hanoi). For this lab, the goal is to move 3 discs from peg 1 to peg 2 using peg 3 as a temporary.  The files we've provided call the hanoi function, and print output using the print function.

#### Part A: Implementation Background

The file hanoi.s is a full implementation. The main program simply sets up the stack pointer and arguments and makes the initial call to hanoi. Hanoi is a recursive routine, taking four arguments:

hanoi(int n, int src, int dest, int temp)

n = number of disc to move ( 1, 3, 7 )
src = number of the source peg (1,2,4)
dest = number of the destination peg (1,2, or 4)
temp = number of the temporary peg (1,2, or 4)

#### Encodings

For this lab we will be using only the LEDs as output:
1. The discs 1,2,3 are encoded in unary. (i.e. 1 = 0001, 2 = 0011, 3 = 0111)
2. The source, destination, and temporary pegs are encoded one-hot. (i.e. A=0001, B=0010, C=0100)

#### Output

hanoi.s contains an implementation of the print function that does the following:

1. uses a two-part pattern to signal the start of a move ( currently 0110 followed by 1001 )
2. displays the disc (0001,0011, or 0111) then sets LEDs to 0000.
3. displays the source peg, (0001, 0010, or 0100)  then sets the LEDs to 0000
4. displays the destination peg, (0001, 0010, or 0100)  then sets the LEDs to 0000
5. uses a two-part pattern to signal the end of a move ( currently 0110 followed by 1001 )

The discs are numbered 1,3,7, (ie. 0001, 0011, 0111)

The pegs are numbered 1, 2, 4  (i.e. 0001, 0010, 01000)

For an example, the LED pattern to move disc 2 from peg 3 to peg 1 would be:

0110
1001
0011
0100
0001
0110
1001

#### Part B: Making hanoi.ucf

To start this step, type the following command in the console:

> do \$DSN\src\Hardware\lab2_make_ucf.do \$DSN\src\Assembly\hanoi.s hanoi.ucf

This will produce a new file called "hanoi.ucf" in \$DSN\src\Hardware\UCFs.

### Phase 2: Synthesis and Implementation

In order to properly synthesize your design, the Flow Settings for your design must be correctly set. Click on the Flow Settings button in the Design Flow Manager and verify that the following settings are correct:
• HDL Synthesis: Synplicity Synplify Premier 8.6 with Design Planner
• Implementation: Xilinx ISE/WebPack 8.2
• Family: Xilinx8x Virtex2P

#### Part A: Setting Synthesis Options:

There are several options that you must set before synthesis can take place. A step by step tutorial that points out each of these settings is available here. Once you have completed setting the options for synthesis, you can run Synplify to begin the process. This is also covered in the tutorial.

1. Verify that pcaddresscomputer.v, controller.v, cpu.bde, Lab2_components.v,  and board.bde are all included for synthesis
2. Right-click the lib378.adf icon and select "Add all files to library"
3. Go to the Generics/Parameters tab and verify that SYNTHESIS is in the "Verilog Compiler Directives" Box
4. Close the options by hitting OK

#### Part B: Synthesis

Be sure that you check the warnings produced by Synplify as some warnings may indicate significant problems with the design that could cause it to fail to implement correctly. A list of warnings grouped by severity can be found here. If you have run into a warning that is not listed on that page and are unsure about whether or not it is going to be a problem, contact one of the course staff.

Now that you have completed synthesis, verify that you have the required files for implementation. You should have a .edf and optionally, a .vm file that have been selected in the file list.

#### Part C: Implementation Options

As with synthesis, you will need to set several options before beginning implementation. A detailed tutorial on setting up and running the implementation process is available here
1. Open the Implementation Options
2. Change the .ucf file to be hanoi.ucf generated in Phase 1
3. Go to the Translate tab and set the "Macro Search Path" to the directory where the core files are stored.
4. Check the following boxes:
• "Do Not Run Post-Map STR" in tab Post-Map STR
• "Do Not Run Post-PAR STR" in tab Post-PAR STR
• "Do Not Run Simulation" in tab Simulation
• "Create Bit File" in tab BitStream
5. Hit OK to confirm the options

### Part D: Implementation

This process can be time consuming, so be prepared to wait anywhere from 10 to 30 minutes for it to complete. For this reason, please do NOT perform implementation on workstations that have XUP boards attached, as this will tie them up when others could be using them.

Once implementation is completed, you will have a .bit file that can be used to program the board.

### Phase 3: Testing

#### Part A: Configuring the board

The final step in getting your design onto the board is using Impact to program the board using the initialized .bit file. A detailed tutorial on using Impact is available here.
1. Logon to a machine with an XUP Board
2. Click-thru the "Found New Hardware Wizard"
3. Open Impact via the XUP programmer icon on the desktop
4. Right-Click the white window and select "Initialize Chain"
1. If step 4 succeeded, go to step 5
2. Otherwise, right-click and select "Cable-Setup"
3. Choose the "Platform Cable USB" in the upper right, hit OK, and retry step 4
5. Hit "Bypass" for the first two windows