CSE 378 Fall 2006

Controller Specifications

This page contains descriptions of each port in the controller that it is your task to implement in this part of the lab. Please review the specifications carefully to prevent issues associated with misunderstanding the purpose or nature of each signal. The descriptions assume "active-high" ports; "asserted" means a value of 1.

Input ports:

Port	Width	Expected behavior
`Func`	6	The 6 low-order bits of the 32-bit instruction. Determines the nature of an R-format instruction.
`Op`	6	The 6 high-order bits of the 32-bit instruction. Determines the nature of most non-R-format instructions.

Output ports:

Port	Width	Expected behavior
`ALUOp`	2	Controls the functionality of the ALU as follows. 00 to force an add (Required for `JAL` and `JALR`) 01 to force a subtract 10 to perform the operation specified in the `Funct` field (`Inst[5:0]`) 11 to perform the operation specified in the `Op` field (`Inst[31:26]`)
`SrcASel`	1	Selects whether to supply register `rs` or the `shamt` field to the ALU. 0 selects the register and 1 selects the `shamt` field.
`SrcBSel`	1	Selects whether to supply register `rt` or the extended immediate field to the ALU. 0 selects the register and 1 selects the immediate.
`Branch`	1	Asserted during branch instructions.
`ExtOp`	2	Controls the extension of the 16-bit immediate field as follows. 00 zero-extends. Necessary for logical I-format operations (e.g. `XORI`.) 01 sign-extends. 10 left-aligns. Necessary for `LUI`. 11 extracts the `shamt` field.
`JAL`	1	Asserted during linked jumps.
`JR`	1	Asserted during jumps to a location specified in a register.
`Jump`	1	Asserted during all jumps.
`Load`	1	Asserted during loads.
`MemSize`	2	Specifies the size of memory instruction as follows. 00 for non-memory instructions 01 for byte instructions 10 for halfword instructions 11 for word instructions
`RegWrite`	1	Asserted when a value should be written to the register file.
`SignedLoad`	1	Asserted when the value from data memory should be sign-extended.
`Store`	1	Asserted during stores.
`WriteToRD`	1	Asserted when the write register is specified in the `rd` field.


	Computer Science & Engineering University of Washington Box 352350 Seattle, WA 98195-2350 (206) 543-1695 voice, (206) 543-2969 FAX [comments to Course Staff]