Lab 3: Data Cache

Description
In this lab, you will build a 16-line data cache that interfaces with the MIPS processor you have developed. This cache will be direct-mapped and write-back. We will provide an updated memory system, and a one-line Instruction Cache to include in your design. .

Software Stage (Both 378 and 378-HW)
You will have to design a working 16-line Data Cache. Your cache must perform correctly in a standalone scenario.

Hardware Stage (378-HW only)
You must demonstrate a working processor with a 16-line Data Cache.

Design Constraints
We will be sticking to the following constraints to make the lab as straightforward as possible:

The cache is direct-mapped.
On a miss, Stall the entire pipeline using the signal DStall
Your Processor must output a MemoryRead signal for each Load instruction. You already have such a signal, so send it out.
We moved the VGA controller addresses, so they fall into the I/O memory space. Download board.h, or replace the lines in your current one with the following:

#define VGA_TEXT_PLANE 0x8000c000 #define VGA_COLOR_PLANE 0x8000e000

Interface Details
The updated memory system makes things rather easy. If you want to read data from memory, set a Read request. At some point later, the memory will respond with valid data. Similiarly, writing data back to memory is a matter of setting Write request.

Here's a cursory overview of the ports your Data Cache provides, and the uses for them:

From Processor: Width Description

DataAddress 32 bits The address in memory the processor is trying to access

DataIn 32 bits Data to be written to the cache/memory from the processor

MemoryWrite 2 bits The Write Enable/Length (2'b01 = byte, 2'b10 = word, 2'b11 = half-word)

MemoryRead 1 bit A signal that says the processor wants to read from the cache/io

To Processor:

DataOut 32 bits The data from the cache to be returned to the processor

DStall 1 bit a signal to tell your processor to stall when you're waiting for data from memory

From Memory/IO:

DCacheDataFromMem 32/128 bits Data returned from the memory system after a read request. NOTE: Only valid when DCacheValid is high

DCacheValid 1 bit This signal will go high once a Read/Write request is complete. You should read in the DataFromMem during this cycle

BypassDataFromMem 32 bits This is data returned from IO devices, make sure you aren't caching it.

To Memory:

DCacheAddrToMem 30/28 bits This is the address (30 or 28 bits depending on the size of your cache lines) that you want to access in the memory.

DCacheDataToMem 32/128 bits This data that you want to write to the memory. It is only read in during the clock cycle when you have WriteRequestToMem asserted.

DCacheReadRequestToMem 1 bit Set this signal high for one clock cycle to signify that you want to perform a read from memory. Then wait for the Valid signal to go high.

DCacheWriteRequestToMem 1 bit Set this signal high for one clock cycle to signify that you want to perform a write to memory. Then wait for Valid to go high.

Requesting a Read/Write to the memory looks something like this:

Note that the signal names aren't quite the same. This was a write to the data cache that resulted in a cache miss. The Stall signal goes high immediately, and then ReadRequest is asserted for one clock cycle. A few cycles pass (the number CAN change), and then Valid is asserted. The Data from memory is written into the correct cache line during that cycle, which then means the cache line is valid and the processor can unstall.

Gotchas!
There are several things you need to consider when doing your processor stalling:

Stalling preserves the current instructions! Stall != Bubble
I/O operations should not cause Data Stalls
All Stalls are not the same

For simplicity, we suggest that you stall the entire pipeline while cache misses are being serviced. Unfortunately, this can cause a problem with I/O operations. If an instruction stall occurs while a memory operation to an I/O address is in the memory stage, that I/O operation will be repeated during the whole stall cycle. To prevent this, zero the MemoryRead and MemoryWrite signals during an IStall. Download the lab2 solution and look a board_1word.bde for an example. Don't change the values in the EX/MEM register!

Implementing Your Cache
Determine the size of cache you want and download the correct board file (see below). In the board file, there is a DCache symbol. It's EMPTY. Double-Click it and you'll be presented with the opportunity to select the implementation type. WE HIGHLY SUGGEST WRITING IT IN VERILOG.

Lib378
Update the library. We have included the following components and possibly fixed issues with some of the symbols:

CacheMemorySystem_1word - Needed if you are using 1-word caches
CacheMemorySystem_4word - " " 4-word " "
ICache_1word - 1-line, 1 word read-only instruction cache
ICache_4word - " " 4 word " "
All sorts of updated memory components included in CacheMemorySystem_*

lib378.zip

Essential Files
CSE378 BIOS Source (updated for lab3)
CSE378 Bootloader Software
Top level board design(v1a) - Contains an instruction cache with 1 line of size 1 word. Has a skeleton for a Data Cache with 16 lines of size 1 word. Just insert your processor into the design and connect the ports.
UCF File (board.ucf)

Lab2 Solution
This zip file is an archived design containing a solution to Lab2. It also includes all the essential files above. There are a few things to note!

We have disabled the stalling mechanism. There are arrows in processor.bde showing this
We added logic in board_1word.bde and board_4word.bde. This prevents the I/O stall issue mentioned above.

Lab2_Solution.zip

Test Files
Test fixture with cache built in

Due Dates
Progress Reports - Sunday, May 27th
Due - Wednesday, May 31st

Turn-in
For the software part of the lab, use ActiveHDL's "Archive Design" command and submit the resulting archive via turnin. Turnin is now available on attu.

Note: You may construct a cache with 4-word lines instead of 1-word lines. This is naturally a more complex endeavor, and not for the faint of heart. If this be your goal, use these files:

Top level board design(v1b)

Computer Science & Engineering
University of Washington
Box 352350
Seattle, WA 98195-2350
(206) 543-1695 voice, (206) 543-2969 FAX
[comments to Shen]

From Processor:	Width	Description
DataAddress	32 bits	The address in memory the processor is trying to access
DataIn	32 bits	Data to be written to the cache/memory from the processor
MemoryWrite	2 bits	The Write Enable/Length (2'b01 = byte, 2'b10 = word, 2'b11 = half-word)
MemoryRead	1 bit	A signal that says the processor wants to read from the cache/io

To Processor:
DataOut	32 bits	The data from the cache to be returned to the processor
DStall	1 bit	a signal to tell your processor to stall when you're waiting for data from memory

From Memory/IO:
DCacheDataFromMem	32/128 bits	Data returned from the memory system after a read request. NOTE: Only valid when DCacheValid is high
DCacheValid	1 bit	This signal will go high once a Read/Write request is complete. You should read in the DataFromMem during this cycle
BypassDataFromMem	32 bits	This is data returned from IO devices, make sure you aren't caching it.

To Memory:
DCacheAddrToMem	30/28 bits	This is the address (30 or 28 bits depending on the size of your cache lines) that you want to access in the memory.
DCacheDataToMem	32/128 bits	This data that you want to write to the memory. It is only read in during the clock cycle when you have WriteRequestToMem asserted.
DCacheReadRequestToMem	1 bit	Set this signal high for one clock cycle to signify that you want to perform a read from memory. Then wait for the Valid signal to go high.
DCacheWriteRequestToMem	1 bit	Set this signal high for one clock cycle to signify that you want to perform a write to memory. Then wait for Valid to go high.