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Active HDL Tips and Tricks
General
- If you are adding an existing file to your design, be sure that you check the "Make local copy" option when selecting the file so that a copy will be made within the design directory.
- If something very strange and unexpected is happenning with your design (such as wires getting renamed strangely or not connecting or Active HDL refusing to compile things or simulate, etc.), it may be helpful to restart Active HDL. If this does make the problem go away, try rebooting the computer, and if that fails, try another computer. If this still fails to resolve it, seek help from one of the course staff. It may also be helpful to create a new version of whatever is broken (for example a block diagram), and simply transfer everything from the old version to the new version through copy/paste.
- SAVE YOUR WORK OFTEN. Active HDL can unexpectedly crash or quit, and if you have not been regularly saving your work, you will have to redo it.
- MAKE BACKUPS. Use the Archive Design functionality to keep at least one or two old versions of your design around in case something goes wrong or a file gets corrupted.
Block Diagrams
- Setting up the environment
- Make sure that the Target HDL for Block Diagrams is set to Verilog. If compiling your block diagrams is producing .edf files rather than .v files, click on the Design menu, then select "Change Target HDL..." and set it to Verilog.
- If you are having trouble getting the components to fit together on the block diagram, click on the Tools menu, then select "Preferences". In the window that appears, select "Block Diagram Editor" from the list on the left, then change the "Grid step" value to 0.025 inches.
- If the area for your block diagram is too small, click on the File menu and select "Page Setup...". Select the "Page Size" tab and adjust the width and height settings as required.
- Parameterized Modules
- Some modules have parameters associated with them. These allow you to change various values, such as the widths of input/output ports. To change the parameters associated with a particular module in a block diagram, right click on the symbol, select Properties, then click on the Parameters tab. Under the Parameters tab, enter the value that you want for a particular parameter in the Actual column.
- If you are using any of the components with a variable width input or output, you MUST specify the width of the bus connecting to the variable width port. Failure to do so will cause the bus to default to a width of 8 bits, which could potentially cause problems later.
- Block Diagram Symbols
- If you have modified the ports on a module that you are using in a block diagram, you can sync them up by right clicking on the symbol in the diagram and selecting "Compare Symbol with Contents...". Select the option to "Update Symbol inside Block Diagram" and then click OK. The symbol on the block diagram will now be updated to match its source.
- Hiding ports on the symbols that you use in block diagrams does not necessarily mean that they have been removed. It is still possible to connect wires to them accidentally. To avoid this, make sure that all hidden ports are placed away from the visible ports, and that you are not placing any other wires near where the hidden ports would be.
- Wiring
- Rather than drawing the individual nets from each of the input/output ports of a module, you can right click on the module, and select "Add Stubs". This will create wires and buses for each port on the module and will name them according to the ports.
- When using the "Add Stubs" feature, make sure that you don't use it with two modules that are too close to each other or the modules may be wired to each other unintentionally.
- If the end of a wire is not connected to anything, it will have a pink square on that end. If you see this on a wire that is supposed to be connected to an input or output port on a symbol, it means that the wire is NOT connected to the symbol.
- Do NOT use a bus to connect two ports of unequal width as ActiveHDL will not handle this correctly. Instead, draw stubs on each port and label them with the same name.
- Query Tool
- The Query tool is your friend. If you are trying to track down a shorted net and want to see what sources are feeding it, simply press Q to bring up the Query tool. Then, enter the name of the net that you are interested in, and it will provide you with a listing of all sources connected to the net as well as all wires that are part of it and what they are connected to.
Verilog
- Make liberal use of parameters. Setting a wire to SHIFT_L is much more descriptive than setting the wire to 3'b001 or something similar. This will become important as you work on your project as it will help you figure out what you wrote.
It is frequently useful to include, or instantiate, a previously written Verilog module in another
Verilog module. For example, the Verilog generated from your various datapath block diagrams includes
statements to instantiate all of the modules whose symbols appear on the block diagrams. The following
is a simple example of module instantiation.
HotDog #( .length(12), .polish_sausage(1) ) foo( .in(bar), .out(baz) );
HotDog is the module type, #( .length(12), .polish_sausage(1) ) is an optional
statement that redefines the parameters length and polish_sausage, foo
is the name of the instantiated module, and .in(bar) means that port in of module
foo is connected to a bus called bar.
The full BNF syntax for module instantiation is on page 192 of Starter's Guide to Verilog 2001,
several copies of which are in CSE 003.
Libraries
- If you update lib378, be sure that you recompile the library. This can be done by making lib378 the active design, then right-clicking on update_lib378.do and selecting "Execute". After you have done this, you can return to your own design and utilize the updated components as part of simulation.
- If you have a design containing a library in the same workspace as your processor design, you can quickly add a library to the list of libraries by right clicking in the Symbols Toolbox and selecting "Select Libraries..." and checking the library that you want included.
Simulation
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