//-----------------------------------------------------------------------------
//
// Title       : phase3_tf
// Design      : lab2
// Author      : Steven
// Company     : University of Washington CSE
//
//-----------------------------------------------------------------------------
//
// File        : phase3_tf.v
// Generated   : Mon Oct 16 16:56:10 2006
// From        : 
// By          : tb_verilog.pl ver. ver 1.2s
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------

`timescale 1ps / 1ps
module phase3_tf;


//Internal signals declarations:
reg RESET;
reg CLK;
reg [31:0]Inst;
wire [31:0]PCOut_actual;
reg [31:0]PCOut;
wire [1:0]MemSize_actual;
reg [1:0]MemSize;
wire [31:0]CPUDataOut_actual;
reg [31:0]CPUDataOut;
reg [31:0]CPUDataIn;
wire [31:0]ALUOut_actual;
reg [31:0]ALUOut;
wire SignedLoad_actual;
reg SignedLoad;
wire Store_actual;
reg Store;
//LOG file declaration.
integer report_file;

//Wait time declaration used in ports monitoring.
//One parameter is declared for every port.
parameter Default_wait_time = 10;
parameter PCOut_WaitTime = Default_wait_time;//WaitTime Parameter for port PCOut
parameter MemSize_WaitTime = Default_wait_time;//WaitTime Parameter for port MemSize
parameter CPUDataOut_WaitTime = Default_wait_time;//WaitTime Parameter for port CPUDataOut
parameter ALUOut_WaitTime = Default_wait_time;//WaitTime Parameter for port ALUOut
parameter SignedLoad_WaitTime = Default_wait_time;//WaitTime Parameter for port SignedLoad
parameter Store_WaitTime = Default_wait_time;//WaitTime Parameter for port Store

//Simulation time
parameter SimulationTime = 64'd2470000 + Default_wait_time + 1;

//Errors counter
integer errors_counter;

//Block of Comparison functions declarations. A separate function for each output port is defined.
//Comparison function for port "PCOut"
function compare_PCOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_PCOut = 1'b1;
		else compare_PCOut = 1'b0;
	end
endfunction
//Comparison function for port "MemSize"
function compare_MemSize;
input [1:0] UUT_output;
input [1:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_MemSize = 1'b1;
		else compare_MemSize = 1'b0;
	end
endfunction
//Comparison function for port "CPUDataOut"
function compare_CPUDataOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_CPUDataOut = 1'b1;
		else compare_CPUDataOut = 1'b0;
	end
endfunction
//Comparison function for port "ALUOut"
function compare_ALUOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_ALUOut = 1'b1;
		else compare_ALUOut = 1'b0;
	end
endfunction
//Comparison function for port "SignedLoad"
function compare_SignedLoad;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_SignedLoad = 1'b1;
		else compare_SignedLoad = 1'b0;
	end
endfunction
//Comparison function for port "Store"
function compare_Store;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Store = 1'b1;
		else compare_Store = 1'b0;
	end
endfunction

// Unit Under Test port map
	cpu UUT (
		.RESET(RESET),
		.CLK(CLK),
		.Inst(Inst),
		.PCOut(PCOut_actual),
		.MemSize(MemSize_actual),
		.CPUDataOut(CPUDataOut_actual),
		.CPUDataIn(CPUDataIn),
		.ALUOut(ALUOut_actual),
		.SignedLoad(SignedLoad_actual),
		.Store(Store_actual));

initial
	begin
		report_file=$fopen("$DSN\\src\\Tests\\phase3_report.log");
		errors_counter = 0;
		#SimulationTime;
		if (errors_counter)
		begin
			$display("Errors were encountered, differences are listed in phase3_report.log");
			$fdisplay(report_file,"Some vectors failed.");
		end
		else
		begin
			$display("All vectors passed.");
			$fdisplay(report_file,"All vectors passed.");
		end
		$fclose(report_file);
		$finish;
	end

//Below code was generated based on waveform file: "E:\my_designs\AndrewH\lab2\compile\phase3_all.vhr"

initial
begin : STIMUL // begin of stimulus process
	#0
	CLK = 1'b0;
	RESET = 1'b1;
	Inst = 32'b00111100000001000000000000000000;
	PCOut = 32'b00000000000000000000000000000000;
	Inst = 32'b00111100000001000000000000000000;
	MemSize = 2'b00;
	CPUDataOut = 32'b00000000000000000000000000000000;
	CPUDataIn = 32'b000000000000000000000000XXXXXXXX;
	ALUOut = 32'b00000000000000000000000000000000;
	SignedLoad = 1'b0;
	Store = 1'b0;
    #340000; //0
	RESET = 1'b0;
    #10000; //340000
	CLK = 1'b1;
	Inst = 32'b00100000100001010000000000011000;
	PCOut = 32'b00000000000000000000000000000100;
	Inst = 32'b00100000100001010000000000011000;
	ALUOut = 32'b00000000000000000000000000011000;
    #20000; //350000
	CLK = 1'b0;
    #20000; //370000
	CLK = 1'b1;
	Inst = 32'b00000000101000000000000000001000;
	PCOut = 32'b00000000000000000000000000001000;
	Inst = 32'b00000000101000000000000000001000;
	CPUDataOut = 32'b00000000000000000000000000000000;
    #20000; //390000
	CLK = 1'b0;
    #20000; //410000
	CLK = 1'b1;
	Inst = 32'b00001100000100000000000000010000;
	PCOut = 32'b00000000000000000000000000011000;
	Inst = 32'b00001100000100000000000000010000;
	ALUOut = 32'b00000000000000000000000000011100;
    #20000; //430000
	CLK = 1'b0;
    #20000; //450000
	CLK = 1'b1;
	Inst = 32'b00000011111000000000000000001000;
	PCOut = 32'b00000000010000000000000001000000;
	Inst = 32'b00000011111000000000000000001000;
    #20000; //470000
	CLK = 1'b0;
    #20000; //490000
	CLK = 1'b1;
	Inst = 32'b00000000000000000000000000000000;
	PCOut = 32'b00000000000000000000000000011100;
	Inst = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00000000000000000000000000000000;
    #20000; //510000
	CLK = 1'b0;
    #20000; //530000
	CLK = 1'b1;
	Inst = 32'b00100000100001100000000001001000;
	PCOut = 32'b00000000000000000000000000100000;
	Inst = 32'b00100000100001100000000001001000;
	ALUOut = 32'b00000000000000000000000001001000;
    #20000; //550000
	CLK = 1'b0;
    #20000; //570000
	CLK = 1'b1;
	Inst = 32'b00000000110000001111100000001001;
	PCOut = 32'b00000000000000000000000000100100;
	Inst = 32'b00000000110000001111100000001001;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00000000000000000000000000101000;
    #20000; //590000
	CLK = 1'b0;
    #20000; //610000
	CLK = 1'b1;
	Inst = 32'b00000011111000000000000000001000;
	PCOut = 32'b00000000000000000000000001001000;
	Inst = 32'b00000011111000000000000000001000;
    #20000; //630000
	CLK = 1'b0;
    #20000; //650000
	CLK = 1'b1;
	Inst = 32'b00000000000000000000000000000000;
	PCOut = 32'b00000000000000000000000000101000;
	Inst = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00000000000000000000000000000000;
    #20000; //670000
	CLK = 1'b0;
    #20000; //690000
	CLK = 1'b1;
	Inst = 32'b00100000100001110000000001010000;
	PCOut = 32'b00000000000000000000000000101100;
	Inst = 32'b00100000100001110000000001010000;
	ALUOut = 32'b00000000000000000000000001010000;
    #20000; //710000
	CLK = 1'b0;
    #20000; //730000
	CLK = 1'b1;
	Inst = 32'b00000000111000000100000000001001;
	PCOut = 32'b00000000000000000000000000110000;
	Inst = 32'b00000000111000000100000000001001;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00000000000000000000000000110100;
    #20000; //750000
	CLK = 1'b0;
    #20000; //770000
	CLK = 1'b1;
	Inst = 32'b00000001000000000000000000001000;
	PCOut = 32'b00000000000000000000000001010000;
	Inst = 32'b00000001000000000000000000001000;
    #20000; //790000
	CLK = 1'b0;
    #20000; //810000
	CLK = 1'b1;
	Inst = 32'b00000000000000000000000000000000;
	PCOut = 32'b00000000000000000000000000110100;
	Inst = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00000000000000000000000000000000;
    #20000; //830000
	CLK = 1'b0;
    #20000; //850000
	CLK = 1'b1;
	Inst = 32'b00001000000100000000000000011000;
	PCOut = 32'b00000000000000000000000000111000;
	Inst = 32'b00001000000100000000000000011000;
    #20000; //870000
	CLK = 1'b0;
    #20000; //890000
	CLK = 1'b1;
	Inst = 32'b00000000000000000000000000000000;
	PCOut = 32'b00000000010000000000000001100000;
	Inst = 32'b00000000000000000000000000000000;
    #20000; //910000
	CLK = 1'b0;
    #20000; //930000
	CLK = 1'b1;
	Inst = 32'b00000000000011111000111101000000;
	PCOut = 32'b00000000010000000000000001100100;
	Inst = 32'b00000000000011111000111101000000;
    #20000; //950000
	CLK = 1'b0;
    #20000; //970000
	CLK = 1'b1;
	Inst = 32'b00000000000010111000000010000010;
	PCOut = 32'b00000000010000000000000001101000;
	Inst = 32'b00000000000010111000000010000010;
    #20000; //990000
	CLK = 1'b0;
    #20000; //1010000
	CLK = 1'b1;
	Inst = 32'b00000011101011111010000000000100;
	PCOut = 32'b00000000010000000000000001101100;
	Inst = 32'b00000011101011111010000000000100;
    #20000; //1030000
	CLK = 1'b0;
    #20000; //1050000
	CLK = 1'b1;
	Inst = 32'b00000000000100011001000101000011;
	PCOut = 32'b00000000010000000000000001110000;
	Inst = 32'b00000000000100011001000101000011;
    #20000; //1070000
	CLK = 1'b0;
    #20000; //1090000
	CLK = 1'b1;
	Inst = 32'b00000000010010111001100000000110;
	PCOut = 32'b00000000010000000000000001110100;
	Inst = 32'b00000000010010111001100000000110;
    #20000; //1110000
	CLK = 1'b0;
    #20000; //1130000
	CLK = 1'b1;
	Inst = 32'b00000000101101001010100000000111;
	PCOut = 32'b00000000010000000000000001111000;
	Inst = 32'b00000000101101001010100000000111;
    #20000; //1150000
	CLK = 1'b0;
    #20000; //1170000
	CLK = 1'b1;
	Inst = 32'b00000010000000000000000000010001;
	PCOut = 32'b00000000010000000000000001111100;
	Inst = 32'b00000010000000000000000000010001;
    #20000; //1190000
	CLK = 1'b0;
    #20000; //1210000
	CLK = 1'b1;
	Inst = 32'b00000000000000001100100000010000;
	PCOut = 32'b00000000010000000000000010000000;
	Inst = 32'b00000000000000001100100000010000;
    #20000; //1230000
	CLK = 1'b0;
    #20000; //1250000
	CLK = 1'b1;
	Inst = 32'b00000010001000000000000000010011;
	PCOut = 32'b00000000010000000000000010000100;
	Inst = 32'b00000010001000000000000000010011;
    #20000; //1270000
	CLK = 1'b0;
    #20000; //1290000
	CLK = 1'b1;
	Inst = 32'b00000000000000001100000000010010;
	PCOut = 32'b00000000010000000000000010001000;
	Inst = 32'b00000000000000001100000000010010;
    #20000; //1310000
	CLK = 1'b0;
    #20000; //1330000
	CLK = 1'b1;
	Inst = 32'b00000001010001010000000000011000;
	PCOut = 32'b00000000010000000000000010001100;
	Inst = 32'b00000001010001010000000000011000;
	CPUDataOut = 32'b00000000000000000000000000011000;
    #20000; //1350000
	CLK = 1'b0;
    #20000; //1370000
	CLK = 1'b1;
	Inst = 32'b00000001010001010000000000011001;
	PCOut = 32'b00000000010000000000000010010000;
	Inst = 32'b00000001010001010000000000011001;
    #20000; //1390000
	CLK = 1'b0;
    #20000; //1410000
	CLK = 1'b1;
	Inst = 32'b00000000100001010100000000100000;
	PCOut = 32'b00000000010000000000000010010100;
	Inst = 32'b00000000100001010100000000100000;
	ALUOut = 32'b00000000000000000000000000011000;
    #20000; //1430000
	CLK = 1'b0;
    #20000; //1450000
	CLK = 1'b1;
	Inst = 32'b00000000100001010100100000100001;
	PCOut = 32'b00000000010000000000000010011000;
	Inst = 32'b00000000100001010100100000100001;
    #20000; //1470000
	CLK = 1'b0;
    #20000; //1490000
	CLK = 1'b1;
	Inst = 32'b00000000100001010101000000100010;
	PCOut = 32'b00000000010000000000000010011100;
	Inst = 32'b00000000100001010101000000100010;
	ALUOut = 32'b11111111111111111111111111101000;
    #20000; //1510000
	CLK = 1'b0;
    #20000; //1530000
	CLK = 1'b1;
	Inst = 32'b00000000100001010101100000100011;
	PCOut = 32'b00000000010000000000000010100000;
	Inst = 32'b00000000100001010101100000100011;
    #20000; //1550000
	CLK = 1'b0;
    #20000; //1570000
	CLK = 1'b1;
	Inst = 32'b00000000101001100110000000100100;
	PCOut = 32'b00000000010000000000000010100100;
	Inst = 32'b00000000101001100110000000100100;
	CPUDataOut = 32'b00000000000000000000000001001000;
	ALUOut = 32'b00000000000000000000000000001000;
    #20000; //1590000
	CLK = 1'b0;
    #20000; //1610000
	CLK = 1'b1;
	Inst = 32'b00000000101001100110100000100101;
	PCOut = 32'b00000000010000000000000010101000;
	Inst = 32'b00000000101001100110100000100101;
	ALUOut = 32'b00000000000000000000000001011000;
    #20000; //1630000
	CLK = 1'b0;
    #20000; //1650000
	CLK = 1'b1;
	Inst = 32'b00000000101001100111000000100110;
	PCOut = 32'b00000000010000000000000010101100;
	Inst = 32'b00000000101001100111000000100110;
	ALUOut = 32'b00000000000000000000000001010000;
    #20000; //1670000
	CLK = 1'b0;
    #20000; //1690000
	CLK = 1'b1;
	Inst = 32'b00000000101001100111100000100111;
	PCOut = 32'b00000000010000000000000010110000;
	Inst = 32'b00000000101001100111100000100111;
	ALUOut = 32'b11111111111111111111111110100111;
    #20000; //1710000
	CLK = 1'b0;
    #20000; //1730000
	CLK = 1'b1;
	Inst = 32'b00000001001010101100000000101010;
	PCOut = 32'b00000000010000000000000010110100;
	Inst = 32'b00000001001010101100000000101010;
	CPUDataOut = 32'b11111111111111111111111111101000;
	ALUOut = 32'b00000000000000000000000000000000;
    #20000; //1750000
	CLK = 1'b0;
    #20000; //1770000
	CLK = 1'b1;
	Inst = 32'b00000001001010101100100000101011;
	PCOut = 32'b00000000010000000000000010111000;
	Inst = 32'b00000001001010101100100000101011;
	ALUOut = 32'b00000000000000000000000000000001;
    #20000; //1790000
	CLK = 1'b0;
    #20000; //1810000
	CLK = 1'b1;
	Inst = 32'b00100000100010000000000000000101;
	PCOut = 32'b00000000010000000000000010111100;
	Inst = 32'b00100000100010000000000000000101;
	CPUDataOut = 32'b00000000000000000000000000011000;
	ALUOut = 32'b00000000000000000000000000000101;
    #20000; //1830000
	CLK = 1'b0;
    #20000; //1850000
	CLK = 1'b1;
	Inst = 32'b00100100100010111111111111111011;
	PCOut = 32'b00000000010000000000000011000000;
	Inst = 32'b00100100100010111111111111111011;
	CPUDataOut = 32'b11111111111111111111111111101000;
	ALUOut = 32'b11111111111111111111111111111011;
    #20000; //1870000
	CLK = 1'b0;
    #20000; //1890000
	CLK = 1'b1;
	Inst = 32'b00101000100011001111111111111111;
	PCOut = 32'b00000000010000000000000011000100;
	Inst = 32'b00101000100011001111111111111111;
	CPUDataOut = 32'b00000000000000000000000000001000;
	ALUOut = 32'b00000000000000000000000000000000;
    #20000; //1910000
	CLK = 1'b0;
    #20000; //1930000
	CLK = 1'b1;
	Inst = 32'b00101100100011011111111111111111;
	PCOut = 32'b00000000010000000000000011001000;
	Inst = 32'b00101100100011011111111111111111;
	CPUDataOut = 32'b00000000000000000000000001011000;
	ALUOut = 32'b00000000000000000000000000000001;
    #20000; //1950000
	CLK = 1'b0;
    #20000; //1970000
	CLK = 1'b1;
	Inst = 32'b00110000101011100000000000001011;
	PCOut = 32'b00000000010000000000000011001100;
	Inst = 32'b00110000101011100000000000001011;
	CPUDataOut = 32'b00000000000000000000000001010000;
	ALUOut = 32'b00000000000000000000000000001000;
    #20000; //1990000
	CLK = 1'b0;
    #20000; //2010000
	CLK = 1'b1;
	Inst = 32'b00111100000001000001000000000000;
	PCOut = 32'b00000000010000000000000011010000;
	Inst = 32'b00111100000001000001000000000000;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00010000000000000000000000000000;
    #20000; //2030000
	CLK = 1'b0;
    #20000; //2050000
	CLK = 1'b1;
	Inst = 32'b00110100101011110000000000001011;
	PCOut = 32'b00000000010000000000000011010100;
	Inst = 32'b00110100101011110000000000001011;
	CPUDataOut = 32'b11111111111111111111111110100111;
	ALUOut = 32'b00000000000000000000000000011011;
    #20000; //2070000
	CLK = 1'b0;
    #20000; //2090000
	CLK = 1'b1;
	Inst = 32'b00111000101110000000000000000110;
	PCOut = 32'b00000000010000000000000011011000;
	Inst = 32'b00111000101110000000000000000110;
	CPUDataOut = 32'b00000000000000000000000000000000;
	ALUOut = 32'b00000000000000000000000000011110;
    #20000; //2110000
	CLK = 1'b0;
    #20000; //2130000
	CLK = 1'b1;
	Inst = 32'b10000000100011000000000000000000;
	PCOut = 32'b00000000010000000000000011011100;
	Inst = 32'b10000000100011000000000000000000;
	MemSize = 2'b01;
	CPUDataOut = 32'b00000000000000000000000000000000;
	CPUDataIn = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX;
	ALUOut = 32'b00010000000000000000000000000000;
	SignedLoad = 1'b1;
    #20000; //2150000
	CLK = 1'b0;
    #20000; //2170000
	CLK = 1'b1;
	Inst = 32'b10000100100010100000000000000010;
	PCOut = 32'b00000000010000000000000011100000;
	Inst = 32'b10000100100010100000000000000010;
	MemSize = 2'b10;
	CPUDataOut = 32'b11111111111111111111111111101000;
	ALUOut = 32'b00010000000000000000000000000010;
    #20000; //2190000
	CLK = 1'b0;
    #20000; //2210000
	CLK = 1'b1;
	Inst = 32'b10001100100010000000000000000000;
	PCOut = 32'b00000000010000000000000011100100;
	Inst = 32'b10001100100010000000000000000000;
	MemSize = 2'b11;
	CPUDataOut = 32'b00000000000000000000000000000101;
	ALUOut = 32'b00010000000000000000000000000000;
	SignedLoad = 1'b0;
    #20000; //2230000
	CLK = 1'b0;
    #20000; //2250000
	CLK = 1'b1;
	Inst = 32'b10010000100010110000000000000000;
	PCOut = 32'b00000000010000000000000011101000;
	Inst = 32'b10010000100010110000000000000000;
	MemSize = 2'b01;
	CPUDataOut = 32'b11111111111111111111111111111011;
	CPUDataIn = 32'b000000000000000000000000XXXXXXXX;
    #20000; //2270000
	CLK = 1'b0;
    #20000; //2290000
	CLK = 1'b1;
	Inst = 32'b10010100100010010000000000000010;
	PCOut = 32'b00000000010000000000000011101100;
	Inst = 32'b10010100100010010000000000000010;
	MemSize = 2'b10;
	CPUDataOut = 32'b00000000000000000000000000011000;
	CPUDataIn = 32'b0000000000000000XXXXXXXXXXXXXXXX;
	ALUOut = 32'b00010000000000000000000000000010;
    #20000; //2310000
	CLK = 1'b0;
    #20000; //2330000
	CLK = 1'b1;
	Inst = 32'b10100000100011110000000000000011;
	PCOut = 32'b00000000010000000000000011110000;
	Inst = 32'b10100000100011110000000000000011;
	MemSize = 2'b01;
	CPUDataOut = 32'b00000000000000000000000000011011;
	CPUDataIn = 32'b000000000000000000000000XXXXXXXX;
	ALUOut = 32'b00010000000000000000000000000011;
	Store = 1'b1;
    #20000; //2350000
	CLK = 1'b0;
    #20000; //2370000
	CLK = 1'b1;
	Inst = 32'b10100100100011110000000000000010;
	PCOut = 32'b00000000010000000000000011110100;
	Inst = 32'b10100100100011110000000000000010;
	MemSize = 2'b10;
	CPUDataIn = 32'b000000000000000000011011XXXXXXXX;
	ALUOut = 32'b00010000000000000000000000000010;
    #20000; //2390000
	CLK = 1'b0;
    #20000; //2410000
	CLK = 1'b1;
	Inst = 32'b10101100100011110000000000000000;
	PCOut = 32'b00000000010000000000000011111000;
	Inst = 32'b10101100100011110000000000000000;
	MemSize = 2'b11;
	CPUDataIn = 32'b0000000000011011XXXXXXXXXXXXXXXX;
	ALUOut = 32'b00010000000000000000000000000000;
    #20000; //2430000
	CLK = 1'b0;
    #20000; //2450000
	CLK = 1'b1;
	Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX;
	PCOut = 32'b00000000010000000000000011111100;
	Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX;
	MemSize = 2'bXX;
	CPUDataOut = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX;
	CPUDataIn = 32'b00000000000000000000000000011011;
	ALUOut = 32'b00000000000000000000000000000000;
	SignedLoad = 1'bx;
	Store = 1'bx;
end // end of stimulus process
	



//Set of always bloks for ports monitoring.
//One block per output port.
//Always block for monitoring port "PCOut";
always @(PCOut or PCOut_actual)
	begin
		#PCOut_WaitTime
		if (compare_PCOut(PCOut,PCOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port PCOut: Expected value is %b, Actual value is %b",PCOut,PCOut_actual);
			$display($realtime,,"ps; Error on port PCOut: Expected value is %b, Actual value is %b",PCOut,PCOut_actual);
		end
	end
//Always block for monitoring port "MemSize";
always @(MemSize or MemSize_actual)
	begin
		#MemSize_WaitTime
		if (compare_MemSize(MemSize,MemSize_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port MemSize: Expected value is %b, Actual value is %b",MemSize,MemSize_actual);
			$display($realtime,,"ps; Error on port MemSize: Expected value is %b, Actual value is %b",MemSize,MemSize_actual);
		end
	end
//Always block for monitoring port "CPUDataOut";
always @(CPUDataOut or CPUDataOut_actual)
	begin
		#CPUDataOut_WaitTime
		if (compare_CPUDataOut(CPUDataOut,CPUDataOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port CPUDataOut: Expected value is %b, Actual value is %b",CPUDataOut,CPUDataOut_actual);
			$display($realtime,,"ps; Error on port CPUDataOut: Expected value is %b, Actual value is %b",CPUDataOut,CPUDataOut_actual);
		end
	end
//Always block for monitoring port "ALUOut";
always @(ALUOut or ALUOut_actual)
	begin
		#ALUOut_WaitTime
		if (compare_ALUOut(ALUOut,ALUOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual);
			$display($realtime,,"ps; Error on port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual);
		end
	end
//Always block for monitoring port "SignedLoad";
always @(SignedLoad or SignedLoad_actual)
	begin
		#SignedLoad_WaitTime
		if (compare_SignedLoad(SignedLoad,SignedLoad_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port SignedLoad: Expected value is %b, Actual value is %b",SignedLoad,SignedLoad_actual);
			$display($realtime,,"ps; Error on port SignedLoad: Expected value is %b, Actual value is %b",SignedLoad,SignedLoad_actual);
		end
	end
//Always block for monitoring port "Store";
always @(Store or Store_actual)
	begin
		#Store_WaitTime
		if (compare_Store(Store,Store_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Store: Expected value is %b, Actual value is %b",Store,Store_actual);
			$display($realtime,,"ps; Error on port Store: Expected value is %b, Actual value is %b",Store,Store_actual);
		end
	end

endmodule